On Mon, Apr 17, 2023 at 9:26 PM Palmer Dabbelt <pal...@rivosinc.com> wrote: > > On Mon, 17 Apr 2023 11:36:51 PDT (-0700), colli...@rivosinc.com wrote: > > This series of patches adds foundational support for RISC-V > > auto-vectorization support. These patches are based on the current upstream > > rvv vector intrinsic support and is not a new implementation. Most of the > > implementation consists of adding the new vector cost model, the > > autovectorization patterns themselves and target hooks. This implementation > > only provides support for integer addition and subtraction as a proof of > > concept. This patch set should not be construed to be feature complete. > > Based on conversations with the community these patches are intended to lay > > the groundwork for feature completion and collaboration within the RISC-V > > community. > > > > These patches are largely based off the work of Juzhe Zhong > > (juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>) of RiVAI. More > > specifically the rvv-next branch at: > > https://github.com/riscv-collab/riscv-gcc.git > > <https://github.com/riscv-collab/riscv-gcc.git>is the foundation of this > > patch set. > > > > As discussed on this list, if these patches are approved they will be > > merged into a "auto-vectorization" branch once gcc-13 branches for release. > > There are two known issues related to crashes (assert failures) associated > > with tree vectorization; one of which I have sent a patch for and have > > received feedback. > > > > Changes in v4: > > > > - Added support for binary integer operations and test cases > > - Fixed bug to support 8-bit integer vectorization > > - Fixed several assert errors related to non-multiple of two vector modes > > > > Changes in v3: > > > > - Removed the cost model and cost hooks based on feedback from Richard > > Biener > > - Used RVV_VUNDEF macro to fix failing patterns > > > > Changes in v2 > > > > - Updated ChangeLog entry to include RiVAI contributions > > - Fixed ChangeLog email formatting > > - Fixed gnu formatting issues in the code > > > > Kevin Lee (2): > > This patch adds a guard for VNx1 vectors that are present in ports > > like riscv. > > This patch supports 8 bit auto-vectorization in riscv. > > > > Michael Collison (8): > > RISC-V: Add new predicates and function prototypes > > RISC-V: autovec: Export policy functions to global scope > > RISC-V:autovec: Add auto-vectorization support functions > > RISC-V:autovec: Add target vectorization hooks > > RISC-V:autovec: Add autovectorization patterns for binary integer > > operations > > RISC-V:autovec: Add autovectorization tests for add & sub > > vect: Verify that GET_MODE_NUNITS is a multiple of 2. > > RISC-V:autovec: Add autovectorization tests for binary integer > > > > gcc/config/riscv/predicates.md | 13 ++ > > gcc/config/riscv/riscv-opts.h | 40 ++++ > > gcc/config/riscv/riscv-protos.h | 14 ++ > > gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++ > > gcc/config/riscv/riscv-vector-builtins.cc | 4 +- > > gcc/config/riscv/riscv-vector-builtins.h | 3 + > > gcc/config/riscv/riscv.cc | 157 ++++++++++++++++ > > gcc/config/riscv/riscv.md | 1 + > > gcc/config/riscv/riscv.opt | 20 ++ > > gcc/config/riscv/vector-auto.md | 79 ++++++++ > > gcc/config/riscv/vector-iterators.md | 2 + > > gcc/config/riscv/vector.md | 4 +- > > .../riscv/rvv/autovec/loop-add-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 +++ > > .../riscv/rvv/autovec/loop-and-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 +++ > > .../riscv/rvv/autovec/loop-div-rv32.c | 27 +++ > > .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 +++ > > .../riscv/rvv/autovec/loop-max-rv32.c | 26 +++ > > .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 +++ > > .../riscv/rvv/autovec/loop-min-rv32.c | 26 +++ > > .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 +++ > > .../riscv/rvv/autovec/loop-mod-rv32.c | 27 +++ > > .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 +++ > > .../riscv/rvv/autovec/loop-mul-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 +++ > > .../riscv/rvv/autovec/loop-or-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 +++ > > .../riscv/rvv/autovec/loop-sub-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 +++ > > .../riscv/rvv/autovec/loop-xor-rv32.c | 25 +++ > > .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 +++ > > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 + > > gcc/tree-vect-data-refs.cc | 2 + > > gcc/tree-vect-slp.cc | 7 +- > > 35 files changed, 1031 insertions(+), 6 deletions(-) > > create mode 100644 gcc/config/riscv/vector-auto.md > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c > > create mode 100644 > > gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c > > Thanks for re-spinning these. I haven't looked at the actual code yet, > but I think there's still a bigger question as to which way we go here: > Juzhe has talked about wanting to make some larger changes, but as per > some IRC discussions at least the type widening (and possible some of > the other bigger generic changes) aren't suitable for trunk yet as we're > still waiting for the test failures to calm down. > > So I think that leaves us with the option of either taking something > like this now, or waiting. I'd prefer to just get things committed to > trunk so we can all work in the same place, but happy to hear if other > folks have comments. > > I certainly don't intend on committing any of this until it's at least > reviewed and folks are OK with the approach. There's still some > testsuite failures to track down for 13 so no big rush on actually > committing things, but a bunch of folks are spinning up on autovec now > so I'd at least like to get agreement as to which direction we're headed > sooner rather than later.
And just to add - the feature that will tell you whether the backend setup is sustainable is vectorization of loads and stores and that's what I'd start with, not plus or minus (that itself might also show obvious issues of course, and without plus or minus but also bit operations most of the testsuite will fail). Richard.
