> > The concept of fractional LMUL is the same as the concept of AArch64's > > partial SVE vectors, > > so they can only access the lowest part, like SVE's partial vector. > > > > We want to spill/restore the exact size of those modes (1/2, 1/4, > > 1/8), so adding dedicated modes for those partial vector modes should > > be unavoidable IMO. > > > > And even if we use sub-vector, we still need to define those partial > > vector types. > > Could you use integer modes for the fractional vectors?
You mean using the scalar integer mode like using (subreg:SI (reg:VNx4SI) 0) to represent LMUL=1/4? (Assume VNx4SI is mode for M1) If so I think it might not be able to model that right - it seems like we are using 32-bits but actually we are using poly_int16(1, 1) * 32 bits. > For computation you can always appropriately limit the LEN? RVV provide zvl*b extension like zvl<N>b (e.g.zvl128b or zvl256b) to guarantee the vector length is at least larger than N bits, but it's just guarantee the minimal length like SVE guarantee the minimal vector length is 128 bits
