From: Charlie Keaney <charlie.kea...@embecosm.com>
Add all ZC* extensions march args tests.
Co-Authored by: Nandni Jamnadas <nandni.jamna...@embecosm.com>
Co-Authored by: Jiawei <jia...@iscas.ac.cn>
Co-Authored by: Mary Bennett <mary.benn...@embecosm.com>
Co-Authored by: Simon Cook <simon.c...@embecosm.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/arch-21.c: New test.
* gcc.target/riscv/zc-zca-arch.c: New test.
* gcc.target/riscv/zc-zcb-arch.c: New test.
* gcc.target/riscv/zc-zcb-m-arch.c: New test.
* gcc.target/riscv/zc-zcb-zba-arch.c: New test.
* gcc.target/riscv/zc-zcb-zbb-arch.c: New test.
* gcc.target/riscv/zc-zcf-arch.c: New test.
* gcc.target/riscv/zc-zcmp-arch.c: New test.
* gcc.target/riscv/zc-zcmpe-arch.c: New test.
* gcc.target/riscv/zc-zcmt-arch.c: New test.
---
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++++
gcc/testsuite/gcc.target/riscv/arch-21.c | 5 +++++
gcc/testsuite/gcc.target/riscv/zc-zca-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c | 9 +++++++++
gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c | 9 +++++++++
11 files changed, 91 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 00000000000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" ""
{ target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c
b/gcc/testsuite/gcc.target/riscv/arch-21.c
new file mode 100644
index 00000000000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" {
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension
supports in rv32 only" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
new file mode 100644
index 00000000000..bcb8321e709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zca -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.sw x9, 32(x10)");
+}
+
+/* { dg-final { scan-assembler "c.sw x9, 32\\(x10\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
new file mode 100644
index 00000000000..54d4dff63ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
new file mode 100644
index 00000000000..f23fe304607
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32im_zcb -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
new file mode 100644
index 00000000000..6b4a8762078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb_zba -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
new file mode 100644
index 00000000000..53f8dba80d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb_zbb -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
new file mode 100644
index 00000000000..dcdadc87b79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcf -mabi=ilp32" } */
+
+int foo()
+{
+ asm("c.flw fa0, 0(a0)");
+}
+
+/* { dg-final { scan-assembler "c.flw fa0, 0\\(a0\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
new file mode 100644
index 00000000000..17c54d6b2af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb_zcmp -mabi=ilp32" } */
+
+int foo()
+{
+ asm("cm.push {ra,s0-s3},-32");
+}
+
+/* { dg-final { scan-assembler "cm.push {ra,s0-s3},-32" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
new file mode 100644
index 00000000000..68547c9a820
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32e_zcb_zcmp -mabi=ilp32e" } */
+
+int foo()
+{
+ asm("cm.push {ra,s0-s3},-32");
+}
+
+/* { dg-final { scan-assembler "cm.push {ra,s0-s3},-32" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
b/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
new file mode 100644
index 00000000000..133de0c250c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32im_zcmt -mabi=ilp32" } */
+
+int foo()
+{
+ asm("cm.jt 0");
+}
+
+/* { dg-final { scan-assembler "cm.jt 0" } } */
--
2.25.1
