On Tue, Mar 14, 2023 at 4:52 PM Hu, Lin1 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> It has regtested on x86_64-pc-linux-gnu. OK for trunk?
I think uros has approved your patch.
>
> Thanks.
> Lin
>
> -----Original Message-----
> From: Uros Bizjak <ubiz...@gmail.com>
> Sent: Tuesday, March 14, 2023 3:05 PM
> To: Hu, Lin1 <lin1...@intel.com>
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao <hongtao....@intel.com>
> Subject: Re: [PATCH] i386:Add missing OPTION_MASK_ISA_AVX512VL in
> i386-builtin.def for VAES builtins
>
> On Tue, Mar 14, 2023 at 7:2 AM Hu, Lin1 <lin1...@intel.com> wrote:
> >
> > The implementation of these builtins requires support for both
> > AVX512VL and VAES. However, the builtins didn't request AVX512VL. As a
> > result, compiling pr109117-1.c with the options -mvaes -mno-avx512vl caused
> > an ICE.
> >
> > This patch aims to fix the bug.
> >
> > gcc/ChangeLog:
> >
> > PR target/109117
> > * config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
> > __builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
> > __builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL.
> >
> > gcc/testsuite/ChangeLog:
> >
> > PR target/109117
> > * gcc.target/i386/pr109117-1.c: New test.
>
> OK.
>
> Thanks,
> Uros.
>
> > ---
> > gcc/config/i386/i386-builtin.def | 8 ++++----
> > gcc/testsuite/gcc.target/i386/pr109117-1.c | 14 ++++++++++++++
> > 2 files changed, 18 insertions(+), 4 deletions(-) create mode 100644
> > gcc/testsuite/gcc.target/i386/pr109117-1.c
> >
> > diff --git a/gcc/config/i386/i386-builtin.def
> > b/gcc/config/i386/i386-builtin.def
> > index f1c295c34f6..17dfe40fac7 100644
> > --- a/gcc/config/i386/i386-builtin.def
> > +++ b/gcc/config/i386/i386-builtin.def
> > @@ -2797,16 +2797,16 @@ BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW,
> > CODE_FOR_avx5124vnniw_vp4dpwssds_mask,
> > BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid,
> > "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int)
> > UNSIGNED_FTYPE_VOID)
> >
> > /* VAES. */
> > -BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi,
> > "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int)
> > V16QI_FTYPE_V16QI_V16QI)
> > +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
> > +CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi",
> > +IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi,
> > "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int)
> > V32QI_FTYPE_V32QI_V32QI) BDESC (0, OPTION_MASK_ISA2_VAES,
> > CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi",
> > IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC
> > (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi,
> > "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16,
> > UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
> > +CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi",
> > +IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi,
> > "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32,
> > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) BDESC (0,
> > OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi,
> > "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64,
> > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0,
> > OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi,
> > "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int)
> > V16QI_FTYPE_V16QI_V16QI)
> > +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
> > +CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi",
> > +IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi,
> > "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int)
> > V32QI_FTYPE_V32QI_V32QI) BDESC (0, OPTION_MASK_ISA2_VAES,
> > CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi",
> > IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC
> > (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi,
> > "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16,
> > UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES,
> > +CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi",
> > +IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
> > BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi,
> > "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32,
> > UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) BDESC (0,
> > OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v64qi,
> > "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64,
> > UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
> >
> > diff --git a/gcc/testsuite/gcc.target/i386/pr109117-1.c
> > b/gcc/testsuite/gcc.target/i386/pr109117-1.c
> > new file mode 100644
> > index 00000000000..87a5c0e7fc9
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/i386/pr109117-1.c
> > @@ -0,0 +1,14 @@
> > +/* PR target/109117 */
> > +/* { dg-do compile } */
> > +/* { dg-options "-mvaes -mno-avx512vl" } */
> > +
> > +typedef char __v16qi __attribute__ ((__vector_size__(16))); typedef
> > +long long __m128i __attribute__((__vector_size__(16),
> > +__aligned__(16))); volatile __v16qi x, y; volatile __m128i res;
> > +
> > +void
> > +foo (void)
> > +{
> > + res = __builtin_ia32_vaesdec_v16qi (x, y); /* { dg-warning "implicit
> > declaration of function" } */
> > +} /* { dg-error "incompatible types when assigning to type" "" {
> > target *-*-* } .-1 } */
> > --
> > 2.31.1
> >
--
BR,
Hongtao
