[PATCH] RISC-V: Fix Bug 109092

[juzhe . zhong]

From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>

This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092.

gcc/ChangeLog:

        * config/riscv/riscv.md: Fix subreg bug.

---
 gcc/config/riscv/riscv.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 371d6838c0b..700f3c28bc3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1364,8 +1364,8 @@
        (zero_extend:DI
            (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
   "TARGET_64BIT && !TARGET_ZBA
-   && !(REG_P (operands[1])
-        && REGNO (operands[1]) == VL_REGNUM)"
+   && !(register_operand (operands[1], SImode)
+        && reg_or_subregno (operands[1]) == VL_REGNUM)"
   "@
    #
    lwu\t%0,%1"
@@ -1747,7 +1747,7 @@
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
     && !(register_operand (operands[1], SImode)
-         && REGNO (operands[1]) == VL_REGNUM)"
+         && reg_or_subregno (operands[1]) == VL_REGNUM)"
   { return riscv_output_move (operands[0], operands[1]); }
   [(set_attr "move_type" 
"move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
    (set_attr "mode" "SI")
-- 
2.36.3