2023-03-02 Michael Collison <colli...@rivosinc.com>
Juzhe Zhong <juzhe.zh...@rivai.ai>
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector-iterators.md (UNSPEC_VADD/UNSPEC_VSUB):
New unspecs for autovectorization patterns.
* config/riscv/vector.md: Remove include of vector-iterators.md
and include vector-auto.md.
---
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/vector-auto.md | 172 +++++++++++++++++++++++++++
gcc/config/riscv/vector-iterators.md | 2 +
gcc/config/riscv/vector.md | 4 +-
4 files changed, 177 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/vector-auto.md
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6c3176042fb..a504ace72e5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -131,6 +131,7 @@
(include "predicates.md")
(include "constraints.md")
(include "iterators.md")
+(include "vector-iterators.md")
;; ....................
;;
diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md
new file mode 100644
index 00000000000..5227a73d96d
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,172 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+;; Contributed by Michael Collison (colli...@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Addition
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vadd.vv
+;; - vadd.vx
+;; - vadd.vi
+;; -------------------------------------------------------------------------
+
+(define_expand "add<mode>3"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "vector_arith_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = emit_vlmax_vsetvl (<MODE>mode);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_add<mode>(operands[0], mask, merge, operands[1],
operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+(define_expand "cond_add<mode>"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:<VM> 1 "register_operand")
+ (match_operand:VI 2 "register_operand")
+ (match_operand:VI 3 "vector_reg_or_const_dup_operand")
+ (match_operand:VI 4 "register_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = operands[4];
+ rtx vl = emit_vlmax_vsetvl (<MODE>mode);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = operands[1];
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_add<mode>(operands[0], mask, merge, operands[2],
operands[3],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+ DONE;
+})
+
+(define_expand "len_add<mode>"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "vector_reg_or_const_dup_operand")
+ (match_operand 3 "p_reg_or_const_csr_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = operands[3];
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_add<mode>(operands[0], mask, merge, operands[1],
operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+ DONE;
+})
+
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Subtraction
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vsub.vv
+;; - vsub.vx
+;; - vadd.vi
+;; - vrsub.vx
+;; - vrsub.vi
+;; -------------------------------------------------------------------------
+
+(define_expand "sub<mode>3"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "register_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = emit_vlmax_vsetvl (<MODE>mode);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_sub<mode>(operands[0], mask, merge, operands[1],
operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+(define_expand "cond_sub<mode>"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:<VM> 1 "register_operand")
+ (match_operand:VI 2 "register_operand")
+ (match_operand:VI 3 "register_operand")
+ (match_operand:VI 4 "register_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = operands[4];
+ rtx vl = emit_vlmax_vsetvl (<MODE>mode);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = operands[1];
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_sub<mode>(operands[0], mask, merge, operands[2],
operands[3],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+(define_expand "len_sub<mode>"
+ [(match_operand:VI 0 "register_operand")
+ (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "register_operand")
+ (match_operand 3 "p_reg_or_const_csr_operand")]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = operands[3];
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_sub<mode>(operands[0], mask, merge, operands[1],
operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 61e141e7b64..af80143ce90 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -34,6 +34,8 @@
UNSPEC_VMULHU
UNSPEC_VMULHSU
+ UNSPEC_VADD
+ UNSPEC_VSUB
UNSPEC_VADC
UNSPEC_VSBC
UNSPEC_VMADC
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 2d4eb8bf1cd..85e531c83ef 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -26,8 +26,6 @@
;; - Auto-vectorization (TBD)
;; - Combine optimization (TBD)
-(include "vector-iterators.md")
-
(define_constants [
(INVALID_ATTRIBUTE 255)
(X0_REGNUM 0)
@@ -350,6 +348,8 @@
(symbol_ref "INTVAL (operands[4])")]
(const_int INVALID_ATTRIBUTE)))
+(include "vector-auto.md")
+
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
;; -----------------------------------------------------------------
--
2.34.1
