This series of patches adds foundational support for RISC-V
autovectorization. These patches are based on the current upstream rvv
vector intrinsic support and is not a new implementation. Most of the
implementation consists of adding the new vector cost model, the
autovectorization patterns themselves and target hooks.
This implementation only provides support for integer addition and
subtraction as a proof of concept.
As discussed on this list, if these patches are approved they will be
merged into a "auto-vectorization" branch once gcc-13 branches for release.
There are two known issues related to crashes (assert failures)
associated with tree vectorization; one of which I have sent a patch for
and have received feedback. I will be sending a patch for the second
issue tomorrow.
gcc/common/config/riscv/riscv-common.cc | 2 +-
gcc/config.gcc | 2 +-
gcc/config/riscv/predicates.md | 13 +
gcc/config/riscv/riscv-cores.def | 14 +-
gcc/config/riscv/riscv-opts.h | 40 ++
gcc/config/riscv/riscv-protos.h | 15 +
gcc/config/riscv/riscv-v.cc | 178 ++++-
gcc/config/riscv/riscv-vector-builtins.cc | 4 +-
gcc/config/riscv/riscv-vector-builtins.h | 2 +
gcc/config/riscv/riscv-vector-cost.cc | 620 ++++++++++++++++++
gcc/config/riscv/riscv-vector-cost.h | 400 +++++++++++
gcc/config/riscv/riscv.cc | 321 ++++++++-
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/riscv.opt | 20 +
gcc/config/riscv/t-riscv | 5 +
gcc/config/riscv/vector-auto.md | 172 +++++
gcc/config/riscv/vector-iterators.md | 2 +
gcc/config/riscv/vector.md | 4 +-
.../riscv/rvv/autovec/loop-add-rv32.c | 24 +
.../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +
.../riscv/rvv/autovec/loop-sub-rv32.c | 24 +
.../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +
22 files changed, 1893 insertions(+), 18 deletions(-)
create mode 100644 gcc/config/riscv/riscv-vector-cost.cc
create mode 100644 gcc/config/riscv/riscv-vector-cost.h
create mode 100644 gcc/config/riscv/vector-auto.md
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
