On Mon, 13 Feb 2023, Jeff Law via Gcc-patches wrote: > 3. The canaonical conditional-zero-or-value assumes the target can do a > generic SEQ/SNE of two register values. As you know, on RISC-V we have > SEQZ/SNEZ. So we've added another fallback path to handle that case in > noce_emit_condzero. You subtract the two values, then you can do an SEQZ/SNEZ > on the result.
NB these machine operations are identical to MIPSr6 SELEQZ and SELNEZ instructions (cf. ISA_HAS_SEL), so why can't we just duplicate what the MIPS backend does? Or did the MIPS backend do something wrong here? Maciej
