From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
simm32_p is used to check constant int value within 32-bit.
It's used in handling SEW = 64 in rv32 system since such constant int
value with 32-bit allow us use vx instruction.
The current implementation of simm32_p is quite ugly and now I figure
out immedate_operand (op, pmode) can help us to check whether the op
is a constant value within 32-bit.
I already have a bunch testcases to test SEW = 64 in rv32 system and
all regression tests are passed with this patch.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (simm32_p):
* config/riscv/riscv-v.cc (simm32_p):
* config/riscv/vector.md:
---
gcc/config/riscv/riscv-protos.h | 1 -
gcc/config/riscv/riscv-v.cc | 10 ----------
gcc/config/riscv/vector.md | 34 ++++++++++++++++-----------------
3 files changed, 17 insertions(+), 28 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 9d8b0b78a06..ee8e903ddf5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -176,7 +176,6 @@ enum tail_policy get_prefer_tail_policy ();
enum mask_policy get_prefer_mask_policy ();
rtx get_avl_type_rtx (enum avl_type);
opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
-extern bool simm32_p (rtx);
extern bool simm5_p (rtx);
extern bool neg_simm5_p (rtx);
#ifdef RTX_CODE
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 600b2e6ecad..dd70bf9b541 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -396,16 +396,6 @@ get_vector_mode (scalar_mode inner_mode, poly_uint64
nunits)
return opt_machine_mode ();
}
-/* Helper functions for handling sew=64 on RV32 system. */
-bool
-simm32_p (rtx x)
-{
- if (!CONST_INT_P (x))
- return false;
- unsigned HOST_WIDE_INT val = UINTVAL (x);
- return val <= 0x7FFFFFFFULL || val >= 0xFFFFFFFF80000000ULL;
-}
-
bool
simm5_p (rtx x)
{
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index dc79aa230bd..b6e67e94f67 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -889,7 +889,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[3]))
+ if (immediate_operand (operands[3], Pmode))
operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[3]));
else
@@ -1479,7 +1479,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
@@ -1572,7 +1572,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
@@ -1665,7 +1665,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
else
@@ -1820,7 +1820,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
else
@@ -1907,7 +1907,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
operands[4] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[4]));
else
@@ -2034,7 +2034,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
@@ -2226,7 +2226,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[3]))
+ if (immediate_operand (operands[3], Pmode))
operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[3]));
else
@@ -2320,7 +2320,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[3]))
+ if (immediate_operand (operands[3], Pmode))
{
if (!rtx_equal_p (operands[3], const0_rtx))
operands[3] = force_reg (Pmode, operands[3]);
@@ -2497,7 +2497,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[2]))
+ if (immediate_operand (operands[2], Pmode))
operands[2] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[2]));
else
@@ -2577,7 +2577,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[2]))
+ if (immediate_operand (operands[2], Pmode))
{
if (!rtx_equal_p (operands[2], const0_rtx))
operands[2] = force_reg (Pmode, operands[2]);
@@ -2738,7 +2738,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[2]))
+ if (immediate_operand (operands[2], Pmode))
operands[2] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[2]));
else
@@ -2815,7 +2815,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[2]))
+ if (immediate_operand (operands[2], Pmode))
{
if (!rtx_equal_p (operands[2], const0_rtx))
operands[2] = force_reg (Pmode, operands[2]);
@@ -3310,7 +3310,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[4]))
+ if (immediate_operand (operands[4], Pmode))
{
if (!rtx_equal_p (operands[4], const0_rtx))
operands[4] = force_reg (Pmode, operands[4]);
@@ -3686,7 +3686,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[5]))
+ if (immediate_operand (operands[5], Pmode))
{
if (!rtx_equal_p (operands[5], const0_rtx))
operands[5] = force_reg (Pmode, operands[5]);
@@ -3739,7 +3739,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[5]))
+ if (immediate_operand (operands[5], Pmode))
{
if (!rtx_equal_p (operands[5], const0_rtx))
operands[5] = force_reg (Pmode, operands[5]);
@@ -4404,7 +4404,7 @@
{
rtx v = gen_reg_rtx (<MODE>mode);
- if (riscv_vector::simm32_p (operands[2]))
+ if (immediate_operand (operands[2], Pmode))
operands[2] = gen_rtx_SIGN_EXTEND (<VEL>mode,
force_reg (Pmode, operands[2]));
else
--
2.36.3
