> > Thank you so much. Kito helped me fix it already. > > RVV instruction patterns can have CSE optimizations now. > What was the issue?
VL and VTYPE isn't listed in fixed register so CSE feel that isn't cheap (See CHEAP_REGNO in cse.cc), but actually it's kind of mistake sett for VL and VTYPE register to non fixed register, it all managed by vsetvl insertion pass, and won't involved into the register allocation process, so it should be set 1 in FIXED_REGISTERS, then CSE pass is happy to cse that after we fix that :) More story behind that is we were trying to rely on RA to manage VL and VTYPE before, and then...we gave up and decided to manage that by ourselves.
