Richard Sandiford <richard.sandif...@arm.com> writes:
> Jakub Jelinek <ja...@redhat.com> writes:
>> On Thu, Jan 12, 2023 at 04:50:07PM +0000, Richard Sandiford wrote:
>>> I'm jumping in here without fully understanding the context, so maybe this
>>> is exactly your point, but: the SIMD/FP DWARF registers are supposed to be
>>> size 8 regardless of which features are enabled. That's already only half
>>> of the hardware register size for base Armv8-A, since Advanced SIMD
>>> registers
>>> are 16 bytes in size.
>>>
>>> So yeah, if we're using the hardware register size then something is wrong.
>>
>> I'm talking about what the following compiles to
>> static unsigned char
>> dwarf_reg_size_table[__LIBGCC_DWARF_FRAME_REGISTERS__+1];
>>
>> void
>> foo (void)
>> {
>> __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
>> }
>> (and therefore what libgcc/unwind-dw2.c (init_dwarf_reg_size_table) as well)
>> with -O2 -fbuilding-libgcc -march=armv8-a vs. -O2 -fbuilding-libgcc
>> -march=armv8-a+sve
>> The former is setting I think [0..31, 46, 48..63, 72..79, 96]=8, [64..71,
>> 80..95]=0
>> (and leaving others untouched, which keeps them 0).
>> While the latter is setting [0..31, 46, 72..79, 96]=8, [64..71, 80..95]=0
>> and [48..63]=cntd
>
> Ah, interesting. So the SIMD/FP registers are OK, but the predicate
> registers are causing a problem.
>
> I think we should set the predicates to size 0 too, like we do for
> call-clobbered FP registers. Predicate registers should never need
> to be represented in CFI.
Done with the patch below. Tested on aarch64-linux-gnu & pushed.
Thanks Jakub for pointing this out.
Richard
gcc/
* config/aarch64/aarch64.cc (aarch64_dwarf_frame_reg_mode): New
function.
(TARGET_DWARF_FRAME_REG_MODE): Define.
gcc/testsuite/
* gcc.target/aarch64/dwarf_reg_size_1.c: New test.
* gcc.target/aarch64/dwarf_reg_size_2.c: Likewise.
---
gcc/config/aarch64/aarch64.cc | 17 ++++++++++++
.../gcc.target/aarch64/dwarf_reg_size_1.c | 27 +++++++++++++++++++
.../gcc.target/aarch64/dwarf_reg_size_2.c | 6 +++++
3 files changed, 50 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 80b71a7b612..2821368756b 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -3443,6 +3443,20 @@ aarch64_debugger_regno (unsigned regno)
return DWARF_FRAME_REGISTERS;
}
+/* Implement TARGET_DWARF_FRAME_REG_MODE. */
+static machine_mode
+aarch64_dwarf_frame_reg_mode (int regno)
+{
+ /* Predicate registers are call-clobbered in the EH ABI (which is
+ ARM_PCS_AAPCS64), so they should not be described by CFI.
+ Their size changes as VL changes, so any values computed by
+ __builtin_init_dwarf_reg_size_table might not be valid for
+ all frames. */
+ if (PR_REGNUM_P (regno))
+ return VOIDmode;
+ return default_dwarf_frame_reg_mode (regno);
+}
+
/* If X is a CONST_DOUBLE, return its bit representation as a constant
integer, otherwise return X unmodified. */
static rtx
@@ -27900,6 +27914,9 @@ aarch64_libgcc_floating_mode_supported_p
#undef TARGET_SCHED_REASSOCIATION_WIDTH
#define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
+#undef TARGET_DWARF_FRAME_REG_MODE
+#define TARGET_DWARF_FRAME_REG_MODE aarch64_dwarf_frame_reg_mode
+
#undef TARGET_PROMOTED_TYPE
#define TARGET_PROMOTED_TYPE aarch64_promoted_type
diff --git a/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
new file mode 100644
index 00000000000..cb7666ddaa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-fbuilding-libgcc" } */
+
+static unsigned char dwarf_reg_size_table[__LIBGCC_DWARF_FRAME_REGISTERS__+1];
+
+int
+main (void)
+{
+ __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
+ /* X0-X31 and SP. */
+ for (int i = 0; i < 32; ++i)
+ if (dwarf_reg_size_table[i] != 8)
+ __builtin_abort ();
+ /* Q0-Q31/Z0-Z31, of which only the low 64 bits of register 8-15
+ are saved. */
+ for (int i = 64; i < 96; ++i)
+ if (dwarf_reg_size_table[i] != (i >= 72 && i < 80 ? 8 : 0))
+ __builtin_abort ();
+ /* P0-P15, which are never saved. */
+ for (int i = 48; i < 63; ++i)
+ if (dwarf_reg_size_table[i] != 0)
+ __builtin_abort ();
+ /* VG */
+ if (dwarf_reg_size_table[46] != 8)
+ __builtin_abort ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
new file mode 100644
index 00000000000..8b7e6d4a717
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/dwarf_reg_size_2.c
@@ -0,0 +1,6 @@
+/* { dg-do run { target aarch64_sve_hw } } */
+/* { dg-options "-fbuilding-libgcc" } */
+
+#pragma GCC target "+sve"
+
+#include "dwarf_reg_size_1.c"
--
2.25.1
