Alexander, (Sorry for the late reply due to holiday vacation).
> On Dec 24, 2022, at 3:10 AM, Alexander Monakov <amona...@ispras.ru> wrote: > > > On Fri, 23 Dec 2022, Qing Zhao wrote: > >> BTW, Why sched1 is not enabled on x86 by default? > > Register allocation is tricky on x86 due to small number of general-purpose > registers, and sched1 can make it even more difficult. I think before register > pressure modeling was added, sched1 could not be enabled because then > allocation > would sometimes fail, and now there's no incentive to enable it, as it is not > so > important for modern x86 CPUs. Perhaps someone else has a more comprehensive > answer. Okay. I see. Thanks for the explanation of the history. > >> Another question is: As discussed in the original bug PR57067: >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57067 The root cause of this >> issue related to the abnormal control flow edges (from setjmp/longjmp) cannot >> be represented correctly at RTL stage, shall we fix this root cause instead? > > You'd need an experienced reviewer to work with you, especially on high-level > design decisions such as "How ABNORMAL_DISPATCHER should be represented on > RTL". > I'm afraid it's not just a matter of applying a small patch in one place. I see. (And I guess so, fixing this is not a trivial work). Qing > > Alexander
