On Fri, Dec 23, 2022 at 05:20:09PM +0100, Richard Biener wrote: > > Am 23.12.2022 um 15:48 schrieb Segher Boessenkool > > <seg...@kernel.crashing.org>: > > None of this belongs in generic code at all imo. At expand time it > > should be expanded to something that works and can be optimised well, > > so not anything with :BLK (which has to be put in memory, something with > > unbounded size cannot be put in registers), not anything specifically > > tailored to any cpu, something nice and regular. Using a subreg (of a > > pseudo!) is the standard way of writing a bitcast. > > > > So generic code would do a (subreg:SF (reg:SI) 0) to express a 32-bit > > integer bitcast to an IEEE SP number, and our machine description should > > make it work nicely. > > There’s also a byte offset in subreg, so (subreg:sf (reg:di) 4) is a Highpart > bitcast.
There are at least six very different kinds of subreg: 0) Lvalue subregs. Most archs have no use for it, and it can be expressed much more clearly and cleanly always. 1) Subregs of mem. Do not use, deprecated. When old reload goes away this will go away. 2) Subregs of hard registers. Do not use, there are much better ways to write subregs of a non-zero byte offset, and for zero offset this is non-canonical RTL. 3) Bitcast subregs. In principle they go from one mode to another mode of the same size (but read on). 4) Paradoxical subregs. A concept completely separate from the rest, different rules for everything, it has to be special cased almost everywhere, it would be better if it was a separate rtx_code imo. 5) Finally, normal subregs, taking a contiguous span of bits from some value. Now, it is invalid to have a subreg of a subreg, so a 3) of a 5) is written as just one subreg, as you say. And a 4) of a 5) is just invalid afaics (and let's not talk about 0)..2) anymore :-) ) > Note whether targets actually support subreg operations needs to be queried > and I’m not sure how subreg with offset validation should work there. But 3) is always valid, no? On pseudos. Segher
