Committed, thanks :)
On Fri, Dec 23, 2022 at 11:33 AM <juzhe.zh...@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Fix contraints.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vle-constraint-1.c: New test.
>
> ---
> gcc/config/riscv/vector.md | 16 +--
> .../riscv/rvv/base/vle-constraint-1.c | 109 ++++++++++++++++++
> 2 files changed, 117 insertions(+), 8 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 98b8f701c92..89810b183fc 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -636,18 +636,18 @@
> ;; 2. (const_vector:VNx1SF repeat [
> ;; (const_double:SF 0.0 [0x0.0p+0])]).
> (define_insn_and_split "@pred_mov<mode>"
> - [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr, m,
> vr, vr")
> + [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr,
> m, vr, vr")
> (if_then_else:V
> (unspec:<VM>
> - [(match_operand:<VM> 1 "vector_mask_operand" " vm, Wc1, vmWc1,
> Wc1, Wc1")
> - (match_operand 4 "vector_length_operand" " rK, rK, rK,
> rK, rK")
> - (match_operand 5 "const_int_operand" " i, i, i,
> i, i")
> - (match_operand 6 "const_int_operand" " i, i, i,
> i, i")
> - (match_operand 7 "const_int_operand" " i, i, i,
> i, i")
> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1,
> vmWc1, Wc1, Wc1")
> + (match_operand 4 "vector_length_operand" " rK, rK,
> rK, rK, rK")
> + (match_operand 5 "const_int_operand" " i, i,
> i, i, i")
> + (match_operand 6 "const_int_operand" " i, i,
> i, i, i")
> + (match_operand 7 "const_int_operand" " i, i,
> i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (match_operand:V 3 "vector_move_operand" " m, m, vr,
> vr, viWc0")
> - (match_operand:V 2 "vector_merge_operand" " 0, vu, vu0,
> vu0, vu0")))]
> + (match_operand:V 3 "vector_move_operand" " m, m,
> vr, vr, viWc0")
> + (match_operand:V 2 "vector_merge_operand" " 0, vu,
> vu0, vu0, vu0")))]
> "TARGET_VECTOR"
> "@
> vle<sew>.v\t%0,%3%p1
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> new file mode 100644
> index 00000000000..b7cf98bfd9f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
> @@ -0,0 +1,109 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "riscv_vector.h"
> +
> +/*
> +** f1:
> +** vsetvli\tzero,4,e32,m1,tu,ma
> +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f1 (float * in, float *out)
> +{
> + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4);
> + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_tu (v, in, 4);
> + __riscv_vse32_v_f32m1 (out, v2, 4);
> +}
> +
> +/*
> +** f2:
> +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> +** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vsetvli\tzero,4,e32,m1,ta,ma
> +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f2 (float * in, float *out)
> +{
> + vbool32_t mask = *(vbool32_t*)in;
> + asm volatile ("":::"memory");
> + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4);
> + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_m (mask, in, 4);
> + __riscv_vse32_v_f32m1 (out, v2, 4);
> +}
> +
> +/*
> +** f3:
> +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
> +** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vsetvli\tzero,4,e32,m1,tu,mu
> +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f3 (float * in, float *out)
> +{
> + vbool32_t mask = *(vbool32_t*)in;
> + asm volatile ("":::"memory");
> + vfloat32m1_t v = __riscv_vle32_v_f32m1 (in, 4);
> + vfloat32m1_t v2 = __riscv_vle32_v_f32m1_tumu (mask, v, in, 4);
> + __riscv_vse32_v_f32m1 (out, v2, 4);
> +}
> +
> +/*
> +** f4:
> +** vsetvli\tzero,4,e8,mf8,tu,ma
> +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f4 (int8_t * in, int8_t *out)
> +{
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4);
> + __riscv_vse8_v_i8mf8 (out, v2, 4);
> +}
> +
> +/*
> +** f5:
> +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> +** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vsetvli\tzero,4,e8,mf8,ta,ma
> +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f5 (int8_t * in, int8_t *out)
> +{
> + vbool64_t mask = *(vbool64_t*)in;
> + asm volatile ("":::"memory");
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4);
> + __riscv_vse8_v_i8mf8 (out, v2, 4);
> +}
> +
> +/*
> +** f6:
> +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
> +** vlm.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vsetvli\tzero,4,e8,mf8,tu,mu
> +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
> +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
> +** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
> +** ret
> +*/
> +void f6 (int8_t * in, int8_t *out)
> +{
> + vbool64_t mask = *(vbool64_t*)in;
> + asm volatile ("":::"memory");
> + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4);
> + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4);
> + __riscv_vse8_v_i8mf8 (out, v2, 4);
> +}
> --
> 2.36.3
>
