Hi Maciej:
It’s not intentionally, I suspect that is because I port from our internal
old gcc branch, will send patch to fix that later, thanks for catching this!
Maciej W. Rozycki <ma...@embecosm.com>於 2022年12月5日 週一，21:05寫道：
> Hi Kito,
>
> I came across this issue while inspecting code and I have been wondering
> what the reason was to downgrade current FMV.X.W and FMW.W.X instructions
> to their older FMV.S.W and FMV.W.S variants here:
>
> On Wed, 10 Aug 2022, Kito Cheng wrote:
>
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 5a0adffb5ce..47e6110767c 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -2308,10 +2310,19 @@ riscv_output_move (rtx dest, rtx src)
> > if (dest_code == REG && GP_REG_P (REGNO (dest)))
> > {
> > if (src_code == REG && FP_REG_P (REGNO (src)))
> > - return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
> > + switch (width)
> > + {
> > + case 2:
> > + /* Using fmv.x.s + sign-extend to emulate fmv.x.h. */
> > + return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16";
> > + case 4:
> > + return "fmv.x.s\t%0,%1";
> > + case 8:
> > + return "fmv.x.d\t%0,%1";
> > + }
>
> and here:
>
> > @@ -2353,18 +2364,24 @@ riscv_output_move (rtx dest, rtx src)
> > return "mv\t%0,%z1";
> >
> > if (FP_REG_P (REGNO (dest)))
> > - {
> > - if (!dbl_p)
> > - return "fmv.w.x\t%0,%z1";
> > - if (TARGET_64BIT)
> > - return "fmv.d.x\t%0,%z1";
> > - /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
> > - gcc_assert (src == CONST0_RTX (mode));
> > - return "fcvt.d.w\t%0,x0";
> > - }
> > + switch (width)
> > + {
> > + case 2:
> > + /* High 16 bits should be all-1, otherwise HW will treated
> > + as a n-bit canonical NaN, but isn't matter for
> softfloat. */
> > + return "fmv.s.x\t%0,%1";
> > + case 4:
> > + return "fmv.s.x\t%0,%z1";
> > + case 8:
> > + if (TARGET_64BIT)
> > + return "fmv.d.x\t%0,%z1";
> > + /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
>
> (Incorrect comment formatting here as well.)
>
> > + gcc_assert (src == CONST0_RTX (mode));
> > + return "fcvt.d.w\t%0,x0";
> > + }
>
> Was it intentional or just an oversight in review? If intentional, I'd
> expect such a change to happen on its own rather than sneaked in with a
> large functional update.
>
> Maciej
>
