On Tue, Dec 6, 2022 at 11:47 AM Jakub Jelinek <ja...@redhat.com> wrote:
>
> Hi!
>
> With -msoft-float we ICE on __bf16 comparisons, because the
> insns we want to use under the hood (cbranchsf4 and cstoresf4)
> after performing the fast extensions aren't available.
>
> The following patch copies the conditions from the c*sf4 expanders
> to the corresponding c*bf4 expanders.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2022-12-06 Jakub Jelinek <ja...@redhat.com>
>
> PR target/107969
> * config/i386/i386.md (cbranchbf4, cstorebf4): Guard expanders
> with the same condition as cbranchsf4 or cstoresf4 expanders.
>
> * gcc.target/i386/pr107969.c: New test.
OK.
Thanks,
Uros.
>
> --- gcc/config/i386/i386.md.jj 2022-12-02 10:28:30.000000000 +0100
> +++ gcc/config/i386/i386.md 2022-12-05 17:21:53.062085995 +0100
> @@ -1667,7 +1667,7 @@ (define_expand "cbranchbf4"
> (const_int 0)])
> (label_ref (match_operand 3))
> (pc)))]
> - ""
> + "TARGET_80387 || (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
> {
> rtx op1 = ix86_expand_fast_convert_bf_to_sf (operands[1]);
> rtx op2 = ix86_expand_fast_convert_bf_to_sf (operands[2]);
> @@ -1702,7 +1702,7 @@ (define_expand "cstorebf4"
> (match_operator 1 "comparison_operator"
> [(reg:CC FLAGS_REG)
> (const_int 0)]))]
> - ""
> + "TARGET_80387 || (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
> {
> rtx op1 = ix86_expand_fast_convert_bf_to_sf (operands[2]);
> rtx op2 = ix86_expand_fast_convert_bf_to_sf (operands[3]);
> --- gcc/testsuite/gcc.target/i386/pr107969.c.jj 2022-12-05 17:27:36.229060068
> +0100
> +++ gcc/testsuite/gcc.target/i386/pr107969.c 2022-12-05 17:27:14.839373669
> +0100
> @@ -0,0 +1,12 @@
> +/* PR target/107969 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fexcess-precision=16 -msoft-float -msse2" } */
> +
> +int i;
> +__bf16 f;
> +
> +void
> +bar (void)
> +{
> + i *= 0 <= f;
> +}
>
> Jakub
>
