gcc/ChangeLog:
* config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix
'vmsr' spacing and reg capitalization.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c:
Update test.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c:
Likewise.
---
gcc/config/arm/vfp.md | 8 ++++----
.../arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 2 +-
.../arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 2 +-
.../arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index d0f423cc3c5..932e4b7447e 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -105,9 +105,9 @@ (define_insn "*thumb2_movhi_vfp"
case 8:
return "vmov%?.f32\t%0, %1\t%@ int";
case 9:
- return "vmsr%?\t P0, %1\t@ movhi";
+ return "vmsr%?\tp0, %1\t@ movhi";
case 10:
- return "vmrs%?\t %0, P0\t@ movhi";
+ return "vmrs%?\t%0, p0\t@ movhi";
default:
gcc_unreachable ();
}
@@ -209,9 +209,9 @@ (define_insn "*thumb2_movhi_fp16"
case 8:
return "vmov%?.f32\t%0, %1\t%@ int";
case 9:
- return "vmsr%?\t P0, %1\t%@ movhi";
+ return "vmsr%?\tp0, %1\t%@ movhi";
case 10:
- return "vmrs%?\t%0, P0\t%@ movhi";
+ return "vmrs%?\t%0, p0\t%@ movhi";
default:
gcc_unreachable ();
}
diff --git
a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
index f3219e2e825..1e57ca40739 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
}
/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
#\[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
diff --git
a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
index 4d093d243fe..f8d77fdfd5b 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
}
/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
#\[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
diff --git
a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
index e796522a49c..8a0e109c70c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c
@@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p)
}
/* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
#\[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
--
2.25.1
