Hello,
On Wed, Nov 16, 2022 at 12:53 PM Kumar, Venkataramanan < venkataramanan.ku...@amd.com> wrote: > [AMD Official Use Only - General] > > Hi, > > > > Top znver table sizes in insn-automata.o: > > > > Before: > > > > 30056 r znver1_fp_min_issue_delay > > 120224 r znver1_fp_transitions > > > > After: > > > > 6720 r znver1_fp_min_issue_delay > > 53760 r znver1_fp_transitions > This looks really promising. I will experiment with the patch for separate znver3 model, but I think we should be able to keep them unified and hopefully get both less code duplicatoin and table sizes. > > > > gcc/ChangeLog: > > > > PR target/87832 > > * config/i386/znver.md: (znver1_fp_op_mul): Correct cycles in > > the reservation. > > (znver1_fp_op_mul_load): Ditto. > > (znver1_mmx_mul): Ditto. > > (znver1_mmx_load): Ditto. > > (znver1_ssemul_ss_ps): Ditto. > > (znver1_ssemul_ss_ps_load): Ditto. > > (znver1_ssemul_avx256_ps): Ditto. > > (znver1_ssemul_avx256_ps_load): Ditto. > > (znver1_ssemul_sd_pd): Ditto. > > (znver1_ssemul_sd_pd_load): Ditto. > > (znver2_ssemul_sd_pd): Ditto. > > (znver2_ssemul_sd_pd_load): Ditto. > > (znver1_ssemul_avx256_pd): Ditto. > > (znver1_ssemul_avx256_pd_load): Ditto. > > (znver1_sseimul): Ditto. > > (znver1_sseimul_avx256): Ditto. > > (znver1_sseimul_load): Ditto. > > (znver1_sseimul_avx256_load): Ditto. > > (znver1_sseimul_di): Ditto. > > (znver1_sseimul_load_di): Ditto. > > --- > > gcc/config/i386/znver.md | 40 ++++++++++++++++++++-------------------- > > 1 file changed, 20 insertions(+), 20 deletions(-) > > > > diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index > > c52f8b532..882f250f1 100644 > > --- a/gcc/config/i386/znver.md > > +++ b/gcc/config/i386/znver.md > > @@ -573,13 +573,13 @@ (define_insn_reservation "znver1_fp_op_mul" 5 > > (and (eq_attr "cpu" "znver1,znver2,znver3") > > (and (eq_attr "type" "fop,fmul") > > (eq_attr "memory" "none"))) > > - "znver1-direct,znver1-fp0*5") > > + "znver1-direct,znver1-fp0") > > > > (define_insn_reservation "znver1_fp_op_mul_load" 12 > > (and (eq_attr "cpu" "znver1,znver2,znver3") > > (and (eq_attr "type" "fop,fmul") > > (eq_attr "memory" "load"))) > > - "znver1-direct,znver1-load,znver1-fp0*5") > > + "znver1-direct,znver1-load,znver1-fp0") > > > > (define_insn_reservation "znver1_fp_op_imul_load" 16 > > (and (eq_attr "cpu" "znver1,znver2,znver3") @@ > -684,13 > > +684,13 @@ (define_insn_reservation "znver1_mmx_mul" 3 > > (and (eq_attr "cpu" "znver1,znver2,znver3") > > (and (eq_attr "type" "mmxmul") > > (eq_attr "memory" "none"))) > > - "znver1-direct,znver1-fp0*3") > > + "znver1-direct,znver1-fp0") > > > > (define_insn_reservation "znver1_mmx_load" 10 > > (and (eq_attr "cpu" "znver1,znver2,znver3") > > (and (eq_attr "type" "mmxmul") > > (eq_attr "memory" "load"))) > > - "znver1-direct,znver1-load,znver1-fp0*3") > > + "znver1-direct,znver1-load,znver1-fp0") > > > > ;; TODO > > (define_insn_reservation "znver1_avx256_log" 1 @@ -1161,7 +1161,7 > > @@ (define_insn_reservation "znver1_ssemul_ss_ps" 3 > > (eq_attr "mode" > > "V8SF,V4SF,SF,V4DF,V2DF,DF"))) > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "none"))) > > - "znver1-direct,(znver1-fp0|znver1-fp1)*3") > > + "znver1-direct,znver1-fp0|znver1-fp1") > > > > (define_insn_reservation "znver1_ssemul_ss_ps_load" 10 > > (and (ior (and (eq_attr "cpu" "znver1") @@ > -1172,47 > > +1172,47 @@ (define_insn_reservation "znver1_ssemul_ss_ps_load" 10 > > (eq_attr "mode" > "V8SF,V4SF,SF"))) > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "load"))) > > - > "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") > > + > > + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") > > > > (define_insn_reservation "znver1_ssemul_avx256_ps" 3 > > (and (eq_attr "cpu" "znver1") > > (and (eq_attr "mode" "V8SF") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "none")))) > > - "znver1-double,(znver1-fp0|znver1-fp1)*3") > > + "znver1-double,znver1-fp0*2|znver1-fp1*2") > > > > (define_insn_reservation "znver1_ssemul_avx256_ps_load" 10 > > (and (eq_attr "cpu" "znver1") > > (and (eq_attr "mode" "V8SF") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "load")))) > > - > "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3") > > + > > + "znver1-double,znver1-load,znver1-fp0*2|znver1-fp1*2") > > > > (define_insn_reservation "znver1_ssemul_sd_pd" 4 > > (and (eq_attr "cpu" "znver1") > > (and (eq_attr "mode" "V2DF,DF") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "none")))) > > - "znver1-direct,(znver1-fp0|znver1-fp1)*4") > > + "znver1-direct,znver1-fp0|znver1-fp1") > > > > (define_insn_reservation "znver1_ssemul_sd_pd_load" 11 > > (and (eq_attr "cpu" "znver1") > > (and (eq_attr "mode" "V2DF,DF") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "load")))) > > - > "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4") > > + > > + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") > > > > (define_insn_reservation "znver2_ssemul_sd_pd" 3 > > (and (eq_attr "cpu" "znver2,znver3") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "none"))) > > - "znver1-direct,(znver1-fp0|znver1-fp1)*3") > > + "znver1-direct,znver1-fp0|znver1-fp1") > > > > (define_insn_reservation "znver2_ssemul_sd_pd_load" 10 > > (and (eq_attr "cpu" "znver2,znver3") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "load"))) > > - > "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3") > > + > > + "znver1-direct,znver1-load,znver1-fp0|znver1-fp1") > > > > > > (define_insn_reservation "znver1_ssemul_avx256_pd" 5 @@ -1220,14 > > +1220,14 @@ (define_insn_reservation "znver1_ssemul_avx256_pd" 5 > > (and (eq_attr "mode" "V4DF") > > (and (eq_attr "type" "ssemul") > > (eq_attr "memory" "none")))) > > - "znver1-double,(znver1-fp0|znver1-fp1)*4") > > + "znver1-double,znver1-fp0*2|znver1-fp1*2") > > Do we need to include "znver1" check here? > If people use nonsential combinations like -mtune=znver1 -march=znver2 this may help a bit. I do it from time to time to see differences between pipelilne models, but it is not too important. > > > > (define_insn_reservation "znver1_sseimul_avx256" 4 > > (and (eq_attr "cpu" "znver1,znver2,znver3") > > (and (eq_attr "mode" "OI") > > (and (eq_attr "type" "sseimul") > > (eq_attr "memory" "none")))) > > - "znver1-double,znver1-fp0*4") > > + "znver1-double,znver1-fp0*2") > > znver1 native path is 128 and znver2/3 has 256 bit paths. > We need to split this into two reservations. One for znver1 and the other > for znver2/3. > isn't it znver2 for 128 and znver3 for 256? The patch looks good. > Patch is OK then :) thanks a lot! Honza > > Regards, > Venkat. > >
