On Tue, 15 Nov 2022, Joshi, Tejas Sanjay wrote:
> > > +;; AVX instructions > > > +(define_insn_reservation "znver4_sse_log" 1 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "sselog,sselog1") > > > + (and (eq_attr "mode" > > > "V4SF,V8SF,V2DF,V4DF") > > > + (eq_attr "memory" "none")))) > > > + "znver4-direct,znver4-fpu") > > > + > > > +(define_insn_reservation "znver4_sse_log_evex" 1 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "sselog,sselog1") > > > + (and (eq_attr "mode" "V16SF,V8DF") > > > + (eq_attr "memory" "none")))) > > > + > > > +"znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3") > > > + > > > > This is an AVX512 instruction, and you're modeling that it occupies two > > ports > > at once and thus has half throughput, but later in the AVX512 section: > > > > > +;; AVX512 instructions > > > +(define_insn_reservation "znver4_sse_mul_evex" 3 > > > + (and (eq_attr "cpu" "znver4") > > > + (and (eq_attr "type" "ssemul") > > > + (and (eq_attr "mode" "V16SF,V8DF") > > > + (eq_attr "memory" "none")))) > > > + "znver4-double,znver4-fpu0|znver4-fpu3") > > > > none of the instructions are modeled this way. If that's on purpose, can you > > add a comment? It's surprising, since generally AVX512 has half throughput > > compared to AVX256 on Zen 4, but the model doesn't seem to reflect that. > > > > +"znver4-direct,znver4-fpu0+znver4-fpu1|znver4-fpu2+znver4-fpu3") > > AVX512 instructions (512-bitwide) occupy 2 consecutive cycles in the pipes > they execute. So, it should be modelled as shown below: > > (define_insn_reservation "znver4_sse_log_evex" 1 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "sselog") > (and (eq_attr "mode" "V16SF,V8DF,XI") > (eq_attr "memory" "none")))) > "znver4-double,(znver4-fpu)*2") I think instead of (znver4-fpu)*2 there should be znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2 assuming the instruction occupies the same pipe on both cycles (your variant models as if it can move from one pipe to another). > (define_insn_reservation "znver4_sse_mul_evex" 3 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "ssemul") > (and (eq_attr "mode" "V16SF,V8DF") > (eq_attr "memory" "none")))) > "znver4-double,(znver4-fpu0|znver4-fpu1)*2") Likewise here, znver4-fpu0*2|znver4-fpu1*2. > Doing this way increased the insn-automata.cc size from 201402 lines to > 212189. Please reevaluate on top of my patches, the impact will be different. > Hope it is a tolerable increase or do you have any suggestions? Please take the corrections above into account. Also I think it's better to use znver4-direct rather than znver4-double for AVX512 instructions, because they are decoded as one uop, not two (it won't make a practical difference due to a "Fix me", but it's a simple improvement). Thanks. Alexander
