On Fri, Nov 17, 2017 at 11:08 AM Wilco Dijkstra <wilco.dijks...@arm.com> wrote: > > Remove SLOW_BYTE_ACCESS given it's confusing, badly named, > badly documented and used incorrectly. Although most targets > define it as 1, there are several targets which confuse it > (based on comments next to it) and set it to 0 since the name > obviously implies it should be 0 when byte accesses are not slow. > > It's hard to tell whether there are targets which actually have > slow *WORD* accesses, where it may be preferable to use narrow > accesses for bitfields. If this is the case (maybe an old 8-bit > target?) then we should consider improving the narrow_volatile_bitfield > callback. That way you could pass the size/alignment/volatile and > decide per bitfield access. > > What do people think?
Seems like this comes up every couple of years even. Looking back I found this older (much) patch https://gcc.gnu.org/legacy-ml/gcc-patches/2006-09/msg00555.html . Which renamed SLOW_BYTE_ACCESS to the correct name and even provided the reason why it still helps x86 but at -Os. I am going to go with HJL's older patch here and convert his target macro into a target hook and look through all of the (active) targets to figure out what is the correct value. I know arm still has it defined incorrectly. MIPS defines it based on MIPS16 which seems wrong too. This will be on my radar for GCC 14. Thanks, Andrew Pinski > > ChangeLog: > 2017-11-17 Wilco Dijkstra <wdijk...@arm.com> > > * config/aarch64/aarch64.h: Remove SLOW_BYTE_ACCESS. > * config/alpha/alpha.h: Likewise. > * config/arc/arc.h: Likewise. > * config/arm/arm.h: Likewise. > * config/avr/avr.h: Likewise. > * config/bfin/bfin.h: Likewise. > * config/c6x/c6x.h: Likewise. > * config/cr16/cr16.h: Likewise. > * config/cris/cris.h: Likewise. > * config/epiphany/epiphany.h: Likewise. > * config/fr30/fr30.h: Likewise. > * config/frv/frv.h: Likewise. > * config/ft32/ft32.h: Likewise. > * config/h8300/h8300.h: Likewise. > * config/i386/i386.h: Likewise. > * config/ia64/ia64.h: Likewise. > * config/iq2000/iq2000.h: Likewise. > * config/lm32/lm32.h: Likewise. > * config/m32c/m32c.h: Likewise. > * config/m32r/m32r.h: Likewise. > * config/m68k/m68k.h: Likewise. > * config/mcore/mcore.h: Likewise. > * config/microblaze/microblaze.h: Likewise. > * config/mips/mips.h: Likewise. > * config/mmix/mmix.h: Likewise. > * config/mn10300/mn10300.h: Likewise. > * config/moxie/moxie.h: Likewise. > * config/msp430/msp430.h: Likewise. > * config/nds32/nds32.h: Likewise. > * config/nios2/nios2.h: Likewise. > * config/nvptx/nvptx.h: Likewise. > * config/pa/pa.h: Likewise. > * config/pdp11/pdp11.h: Likewise. > * config/powerpcspe/powerpcspe.h: Likewise. > * config/riscv/riscv.h: Likewise. > * config/rl78/rl78.h: Likewise. > * config/rs6000/rs6000.h: Likewise. > * config/rx/rx.h: Likewise. > * config/s390/s390.h: Likewise. > * config/sh/sh.h: Likewise. > * config/sparc/sparc.h: Likewise. > * config/spu/spu.h: Likewise. > * config/stormy16/stormy16.h: Likewise. > * config/tilegx/tilegx.h: Likewise. > * config/tilepro/tilepro.h: Likewise. > * config/v850/v850.h: Likewise. > * config/vax/vax.h: Likewise. > * config/visium/visium.h: Likewise. > * config/xtensa/xtensa.h: Likewise. > * doc/tm.texi: Likewise. > * doc/tm.texi.in: Likewise. > * dojump.c: Likewise. > * stor-layout.c: Likewise. > -- > > diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h > index > d8f4d129a02fb89eb00d256aba8c4764d6026078..c509306852585e20e5ab1bd24648eabef39159b0 > 100644 > --- a/gcc/config/aarch64/aarch64.h > +++ b/gcc/config/aarch64/aarch64.h > @@ -769,10 +769,6 @@ typedef struct > if given data not on the nominal alignment. */ > #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN > > -/* Contrary to all documentation, this enables wide bitfield accesses, > - which results in better code when accessing multiple bitfields. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define NO_FUNCTION_CSE 1 > > /* Specify the machine mode that the hardware addresses have. > diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h > index > 257c1de2422b69a0fbb2810ebee455b4088a0a57..42529d7bcc16cb116961a16aeac5b8ca9881035f > 100644 > --- a/gcc/config/alpha/alpha.h > +++ b/gcc/config/alpha/alpha.h > @@ -770,15 +770,6 @@ do { > \ > On the Alpha we have plenty of registers, so use TImode. */ > #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) > > -/* Nonzero if access to memory by bytes is no faster than for words. > - Also nonzero if doing byte operations (specifically shifts) in registers > - is undesirable. > - > - On the Alpha, we want to not use the byte operation and instead use > - masking operations to access fields; these will save instructions. */ > - > -#define SLOW_BYTE_ACCESS 1 > - > /* Define if operations between registers always perform the operation > on the full register even if a narrower mode is specified. */ > #define WORD_REGISTER_OPERATIONS 1 > diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h > index > ec28d619d7c9acaaf438826e2a56e0f64b9de17b..a28dc80ea27e24c7589cdc2b77729c056a2ccb77 > 100644 > --- a/gcc/config/arc/arc.h > +++ b/gcc/config/arc/arc.h > @@ -976,12 +976,6 @@ arc_select_cc_mode (OP, X, Y) > (BRANCH_COST (optimize_function_for_speed_p (cfun), \ > false) > 9) > > -/* Nonzero if access to memory by bytes is slow and undesirable. > - For RISC chips, it means that access to memory by bytes is no > - better than access by words when possible, so grab a whole word > - and maybe make use of that. */ > -#define SLOW_BYTE_ACCESS 0 > - > /* Define this macro if it is as good or better to call a constant > function address than to call an address kept in a register. */ > /* On the ARC, calling through registers is slow. */ > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index > b189951c934e327c88cc5893e9629515c9c39013..80f8da69e0829279520ef6c272fee88a94debc56 > 100644 > --- a/gcc/config/arm/arm.h > +++ b/gcc/config/arm/arm.h > @@ -1874,9 +1874,6 @@ enum arm_auto_incmodes > ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ > : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS 0 > - > /* Immediate shift counts are truncated by the output routines (or was it > the assembler?). Shift counts in a register are truncated by ARM. Note > that the native compiler puts too large (> 32) immediate shift counts > diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h > index > 2272df4afcc1ae02883434767149ae7ac72c94b3..68124845adbc440f0e5a4e2f9e6b467c6e2be63d > 100644 > --- a/gcc/config/avr/avr.h > +++ b/gcc/config/avr/avr.h > @@ -355,8 +355,6 @@ typedef struct avr_args > #define BRANCH_COST(speed_p, predictable_p) \ > (avr_branch_cost + (reload_completed ? 4 : 0)) > > -#define SLOW_BYTE_ACCESS 0 > - > #define NO_FUNCTION_CSE 1 > > #define REGISTER_TARGET_PRAGMAS() \ > diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h > index > e15a05d8784e3e4c56a9055a6047599f8a0e2cea..701ebcd470d3c4e796e75ed81f9bdad80d1490ae > 100644 > --- a/gcc/config/bfin/bfin.h > +++ b/gcc/config/bfin/bfin.h > @@ -797,23 +797,6 @@ typedef struct { > > #define MOVE_RATIO(speed) 5 > > -/* STORAGE LAYOUT: target machine storage layout > - Define this macro as a C expression which is nonzero if accessing > - less than a word of memory (i.e. a `char' or a `short') is no > - faster than accessing a word of memory, i.e., if such access > - require more than one instruction or if there is no difference in > - cost between byte and (aligned) word loads. > - > - When this macro is not defined, the compiler will access a field by > - finding the smallest containing object; when it is defined, a > - fullword load will be used if alignment permits. Unless bytes > - accesses are faster than word accesses, using word accesses is > - preferable since it may eliminate subsequent memory access if > - subsequent accesses occur to other fields in the same word of the > - structure, but to different bytes. */ > -#define SLOW_BYTE_ACCESS 0 > -#define SLOW_SHORT_ACCESS 0 > - > /* Define this if most significant bit is lowest numbered > in instructions that operate on numbered bit-fields. */ > #define BITS_BIG_ENDIAN 0 > diff --git a/gcc/config/c6x/c6x.h b/gcc/config/c6x/c6x.h > index > 233ac13fc8c5eee3f46095a7d35862de7b912ffb..e38a690f8f4a113c76c926821af5ad334983ca69 > 100644 > --- a/gcc/config/c6x/c6x.h > +++ b/gcc/config/c6x/c6x.h > @@ -394,8 +394,6 @@ struct GTY(()) machine_function > /* Costs. */ > #define NO_FUNCTION_CSE 1 > > -#define SLOW_BYTE_ACCESS 0 > - > #define BRANCH_COST(speed_p, predictable_p) 6 > > > diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h > index > b0ad34f70ce24fc7d34659af3656cc7fd51f6387..643f672346e79bac71572926ac544be40324928c > 100644 > --- a/gcc/config/cr16/cr16.h > +++ b/gcc/config/cr16/cr16.h > @@ -440,8 +440,6 @@ struct cumulative_args > /* Assume best case (branch predicted). */ > #define BRANCH_COST(speed_p, predictable_p) 2 > > -#define SLOW_BYTE_ACCESS 1 > - > /* It is as good or better to call a constant function address than to > call an address kept in a register. */ > #define NO_FUNCTION_CSE 1 > diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h > index > 892a3724393de372e37f919e8c56dc8df2861463..58d8327b06005f28ab2b94852f171879e506daca > 100644 > --- a/gcc/config/cris/cris.h > +++ b/gcc/config/cris/cris.h > @@ -770,8 +770,6 @@ struct cum_args {int regs;}; > BRANCH_COST is the best in the range (1, 2, 3), tested with gcc-2.7.2 > with testcases ipps and gcc, giving smallest and fastest code. */ > > -#define SLOW_BYTE_ACCESS 0 > - > /* This is the threshold *below* which inline move sequences of > word-length sizes will be emitted. The "9" will translate to > (9 - 1) * 4 = 32 bytes maximum moved, but using 16 instructions > diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h > index > c0767b4642ad15b470e55f87b49db6148c8c2c1f..ddda3b741840312f802f384d8e1fe9dc5d3cade4 > 100644 > --- a/gcc/config/epiphany/epiphany.h > +++ b/gcc/config/epiphany/epiphany.h > @@ -650,12 +650,6 @@ typedef struct GTY (()) machine_function > #define BRANCH_COST(speed_p, predictable_p) \ > (speed_p ? epiphany_branch_cost : 1) > > -/* Nonzero if access to memory by bytes is slow and undesirable. > - For RISC chips, it means that access to memory by bytes is no > - better than access by words when possible, so grab a whole word > - and maybe make use of that. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define this macro if it is as good or better to call a constant > function address than to call an address kept in a register. */ > /* On the EPIPHANY, calling through registers is slow. */ > diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h > index > 8bcabf59299adc7e9f1b56d40498c39f3e21e255..4645c78457118a45b1ca4aac3b75ef4c1f50bb2d > 100644 > --- a/gcc/config/fr30/fr30.h > +++ b/gcc/config/fr30/fr30.h > @@ -622,19 +622,6 @@ enum reg_class > /*}}}*/ > /*{{{ Describing Relative Costs of Operations */ > > -/* Define this macro as a C expression which is nonzero if accessing less > than > - a word of memory (i.e. a `char' or a `short') is no faster than accessing > a > - word of memory, i.e., if such access require more than one instruction or > if > - there is no difference in cost between byte and (aligned) word loads. > - > - When this macro is not defined, the compiler will access a field by > finding > - the smallest containing object; when it is defined, a fullword load will > be > - used if alignment permits. Unless bytes accesses are faster than word > - accesses, using word accesses is preferable since it may eliminate > - subsequent memory access if subsequent accesses occur to other fields in > the > - same word of the structure, but to different bytes. */ > -#define SLOW_BYTE_ACCESS 1 > - > /*}}}*/ > /*{{{ Dividing the output into sections. */ > > diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h > index > 7403e1ae62103b7dd42d1a8da289d2db6a37df1f..13f0c23200d7292c3f8b58622208ee5f62dec1c0 > 100644 > --- a/gcc/config/frv/frv.h > +++ b/gcc/config/frv/frv.h > @@ -1410,19 +1410,6 @@ __asm__("\n" > \ > default; other values are interpreted relative to that. */ > #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int > > -/* Define this macro as a C expression which is nonzero if accessing less > than > - a word of memory (i.e. a `char' or a `short') is no faster than accessing > a > - word of memory, i.e., if such access require more than one instruction or > if > - there is no difference in cost between byte and (aligned) word loads. > - > - When this macro is not defined, the compiler will access a field by > finding > - the smallest containing object; when it is defined, a fullword load will > be > - used if alignment permits. Unless bytes accesses are faster than word > - accesses, using word accesses is preferable since it may eliminate > - subsequent memory access if subsequent accesses occur to other fields in > the > - same word of the structure, but to different bytes. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define this macro if it is as good or better to call a constant function > address than to call an address kept in a register. */ > #define NO_FUNCTION_CSE 1 > diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h > index > 8bb0d399a0c2f08e2246120aa92a5f11b0731bfb..487b175e321e52961c25c8fbe286eb603e5156f3 > 100644 > --- a/gcc/config/ft32/ft32.h > +++ b/gcc/config/ft32/ft32.h > @@ -286,11 +286,6 @@ enum reg_class > > #define BRANCH_COST(speed_p, predictable_p) 2 > > -/* Define this macro as a C expression which is nonzero if accessing > - less than a word of memory (i.e. a `char' or a `short') is no > - faster than accessing a word of memory. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define STORE_FLAG_VALUE 1 > > #define MOVE_RATIO(speed) ((speed) ? 6 : 2) > diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h > index > 9ba82a76ab9275e891f1eeadaa14551488108b21..e98ce5e0bb7a56483d9a9b2557bb1f416c28a37d > 100644 > --- a/gcc/config/h8300/h8300.h > +++ b/gcc/config/h8300/h8300.h > @@ -546,9 +546,6 @@ struct cum_arg > #define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2) > #define MAX_MOVE_MAX 4 > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS TARGET_SLOWBYTE > - > /* Define if shifts truncate the shift count > which implies one can omit a sign-extension or zero-extension > of a shift count. */ > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > index > bc601c8e6f8739d026292fee1a16c0718f55d852..6e761f37139eee1a02149130ce71918da311ee05 > 100644 > --- a/gcc/config/i386/i386.h > +++ b/gcc/config/i386/i386.h > @@ -1958,25 +1958,6 @@ do { > \ > mode that should actually be used. We allow pairs of registers. */ > #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) > > -/* Define this macro as a C expression which is nonzero if accessing > - less than a word of memory (i.e. a `char' or a `short') is no > - faster than accessing a word of memory, i.e., if such access > - require more than one instruction or if there is no difference in > - cost between byte and (aligned) word loads. > - > - When this macro is not defined, the compiler will access a field by > - finding the smallest containing object; when it is defined, a > - fullword load will be used if alignment permits. Unless bytes > - accesses are faster than word accesses, using word accesses is > - preferable since it may eliminate subsequent memory access if > - subsequent accesses occur to other fields in the same word of the > - structure, but to different bytes. */ > - > -#define SLOW_BYTE_ACCESS 0 > - > -/* Nonzero if access to memory by shorts is slow and undesirable. */ > -#define SLOW_SHORT_ACCESS 0 > - > /* Define this macro if it is as good or better to call a constant > function address than to call an address kept in a register. > > diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h > index > eceab5f23b661a2c3da46c1e649561e081e65f91..fddc35ebe324509a8617feff808deafa8effa6fb > 100644 > --- a/gcc/config/ia64/ia64.h > +++ b/gcc/config/ia64/ia64.h > @@ -1073,12 +1073,6 @@ do { > \ > > #define BRANCH_COST(speed_p, predictable_p) 6 > > -/* Define this macro as a C expression which is nonzero if accessing less > than > - a word of memory (i.e. a `char' or a `short') is no faster than accessing > a > - word of memory. */ > - > -#define SLOW_BYTE_ACCESS 1 > - > /* Define this macro if it is as good or better to call a constant function > address than to call an address kept in a register. > > diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h > index > 72122e27577660e8e623418fea216c75f554ae0b..88380602fdf792735e46ba6949cc4c2079801636 > 100644 > --- a/gcc/config/iq2000/iq2000.h > +++ b/gcc/config/iq2000/iq2000.h > @@ -363,8 +363,6 @@ typedef struct iq2000_args > > #define BRANCH_COST(speed_p, predictable_p) 2 > > -#define SLOW_BYTE_ACCESS 1 > - > #define NO_FUNCTION_CSE 1 > > #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ > diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h > index > 8f2035455ae856f6923bd768e691dab56c71c01c..4f9f4739ef1a5b85b02faebdffb3e9546a645155 > 100644 > --- a/gcc/config/lm32/lm32.h > +++ b/gcc/config/lm32/lm32.h > @@ -332,8 +332,6 @@ enum reg_class > /* Costs. */ > /*---------*/ > > -#define SLOW_BYTE_ACCESS 1 > - > #define NO_FUNCTION_CSE 1 > > #define BRANCH_COST(speed_p, predictable_p) 4 > diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h > index > 4bf67fb9c6726c7f2a6865431084b3eb235d6afa..512970d5936c279d4b246c98672952c5c5094883 > 100644 > --- a/gcc/config/m32c/m32c.h > +++ b/gcc/config/m32c/m32c.h > @@ -171,7 +171,6 @@ machine_function; > #define PCC_BITFIELD_TYPE_MATTERS 0 > > #define STRICT_ALIGNMENT 0 > -#define SLOW_BYTE_ACCESS 1 > > /* Layout of Source Language Data Types */ > > diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h > index > 0fa4c5f24e17ff2512c2dd13873261f71c4129b4..8bdc48fbf1e118e0535a44edd699360a2300cdfc > 100644 > --- a/gcc/config/m32r/m32r.h > +++ b/gcc/config/m32r/m32r.h > @@ -705,12 +705,6 @@ L2: .word STATIC > we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ > #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1) > > -/* Nonzero if access to memory by bytes is slow and undesirable. > - For RISC chips, it means that access to memory by bytes is no > - better than access by words when possible, so grab a whole word > - and maybe make use of that. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define this macro if it is as good or better to call a constant > function address than to call an address kept in a register. */ > #define NO_FUNCTION_CSE 1 > diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h > index > 97693cbf54984a53aa6c35061ca723dae6d1a7b3..25d3082489bcaebb903e58b50f92be66df18b5bb > 100644 > --- a/gcc/config/m68k/m68k.h > +++ b/gcc/config/m68k/m68k.h > @@ -662,7 +662,6 @@ __transfer_from_trampoline () > \ > > #define DEFAULT_SIGNED_CHAR 1 > #define MOVE_MAX 4 > -#define SLOW_BYTE_ACCESS 0 > > /* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */ > #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) > diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h > index > 50d087c1cd5255ef4c3f19c3f73ac3958c8e92bc..b8164ebd6ec49e8298baf06355e17aad361ceb4a > 100644 > --- a/gcc/config/mcore/mcore.h > +++ b/gcc/config/mcore/mcore.h > @@ -529,9 +529,6 @@ extern const enum reg_class > regno_reg_class[FIRST_PSEUDO_REGISTER]; > done, UNKNOWN if none. */ > #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES > - > /* Shift counts are truncated to 6-bits (0 to 63) instead of the expected > 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this > target. */ > diff --git a/gcc/config/microblaze/microblaze.h > b/gcc/config/microblaze/microblaze.h > index > 59cc1cc2e37b7b8c49a56def5f45db261469f579..72340068583bb0b143f506458ea3c82ad821c230 > 100644 > --- a/gcc/config/microblaze/microblaze.h > +++ b/gcc/config/microblaze/microblaze.h > @@ -537,8 +537,6 @@ typedef struct microblaze_args > #define MOVE_MAX 4 > #define MAX_MOVE_MAX 8 > > -#define SLOW_BYTE_ACCESS 1 > - > /* sCOND operations return 1. */ > #define STORE_FLAG_VALUE 1 > > diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h > index > bea2ce844ce9ebc2ab2ea5d1e12616897d5ff65b..9ccf17200f755127b41bf66db7637a67470c34c8 > 100644 > --- a/gcc/config/mips/mips.h > +++ b/gcc/config/mips/mips.h > @@ -2617,19 +2617,6 @@ typedef struct mips_args { > /* We don't modify it for MSA as it is only used by the classic reload. */ > #define MAX_MOVE_MAX 8 > > -/* Define this macro as a C expression which is nonzero if > - accessing less than a word of memory (i.e. a `char' or a > - `short') is no faster than accessing a word of memory, i.e., if > - such access require more than one instruction or if there is no > - difference in cost between byte and (aligned) word loads. > - > - On RISC machines, it tends to generate better code to define > - this as 1, since it avoids making a QI or HI mode register. > - > - But, generating word accesses for -mips16 is generally bad as shifts > - (often extended) would be needed for byte accesses. */ > -#define SLOW_BYTE_ACCESS (!TARGET_MIPS16) > - > /* Standard MIPS integer shifts truncate the shift amount to the > width of the shifted operand. However, Loongson vector shifts > do not truncate the shift amount at all. */ > diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h > index > 2ee3592f3c8d1f0d737f3bb30d10834737374db8..86984cc383e33d27880ece3f0a079852bab4af28 > 100644 > --- a/gcc/config/mmix/mmix.h > +++ b/gcc/config/mmix/mmix.h > @@ -575,9 +575,6 @@ typedef struct { int regs; int lib; } CUMULATIVE_ARGS; > > /* Node: Costs */ > > -#define SLOW_BYTE_ACCESS 0 > - > - > /* Node: Sections */ > > /* This must be a constant string, since it's used in crtstuff.c. */ > diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h > index > b074540f7b1902aa258174a72fcb11b99049056c..8aa1861f9b5f6a240904e980a393f3338381330a > 100644 > --- a/gcc/config/mn10300/mn10300.h > +++ b/gcc/config/mn10300/mn10300.h > @@ -547,10 +547,6 @@ do { > \ > #define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y) > #define REVERSIBLE_CC_MODE(MODE) 0 > > -/* Nonzero if access to memory by bytes or half words is no faster > - than accessing full words. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define NO_FUNCTION_CSE 1 > > /* According expr.c, a value of around 6 should minimize code size, and > diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h > index > 3742967d01c67b03483799c64b2906f1197ed17f..836f9e89586bb9ba2b37c16f08cf54625084ba02 > 100644 > --- a/gcc/config/moxie/moxie.h > +++ b/gcc/config/moxie/moxie.h > @@ -273,11 +273,6 @@ enum reg_class > /* Alignment required for a function entry point, in bits. */ > #define FUNCTION_BOUNDARY 16 > > -/* Define this macro as a C expression which is nonzero if accessing > - less than a word of memory (i.e. a `char' or a `short') is no > - faster than accessing a word of memory. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Number of storage units in a word; normally the size of a > general-purpose register, a power of two from 1 or 8. */ > #define UNITS_PER_WORD 4 > diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h > index > d422725914822425c35e2ac91b920f39416143d8..e25b168802bf077559ba6e5ad214d5e94b8f4947 > 100644 > --- a/gcc/config/msp430/msp430.h > +++ b/gcc/config/msp430/msp430.h > @@ -202,8 +202,6 @@ extern const char * msp430_select_hwmult_lib (int, const > char **); > > #define RETURN_ADDR_RTX(COUNT, FA) \ > msp430_return_addr_rtx (COUNT) > - > -#define SLOW_BYTE_ACCESS 0 > > > /* Register Usage */ > diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h > index > 6954eec17076799e87cee84289b8992b3876eb79..fc9628ca84a7ad15d6d4432c76fa6070fb4a28a1 > 100644 > --- a/gcc/config/nds32/nds32.h > +++ b/gcc/config/nds32/nds32.h > @@ -821,8 +821,6 @@ enum reg_class > other values are interpreted relative to that. */ > #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0) > > -#define SLOW_BYTE_ACCESS 1 > - > #define NO_FUNCTION_CSE 1 > > > diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h > index > 9fdff024cd859495160b3aa31cc80c08dd3f9258..3f0ec97693b25618ad2953e639ac39bd71dbf3de > 100644 > --- a/gcc/config/nios2/nios2.h > +++ b/gcc/config/nios2/nios2.h > @@ -323,7 +323,6 @@ typedef struct nios2_args > > /* Describing Relative Costs of Operations. */ > #define MOVE_MAX 4 > -#define SLOW_BYTE_ACCESS 1 > > /* It is as good to call a constant function address as to call an address > kept in a register. */ > diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h > index > f81b9e2ae697753bf599ca523d4fc3b89ff0ca53..6cfdbc275e5ae07bc3ab44db9e5133f890b78606 > 100644 > --- a/gcc/config/nvptx/nvptx.h > +++ b/gcc/config/nvptx/nvptx.h > @@ -223,7 +223,6 @@ struct GTY(()) machine_function > /* Costs. */ > > #define NO_FUNCTION_CSE 1 > -#define SLOW_BYTE_ACCESS 0 > #define BRANCH_COST(speed_p, predictable_p) 6 > > /* Assembler Format. */ > diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h > index > 7bd1f112471ce4268b8a4229cdcdd3cf36c5a37a..3413da7c700439b1637afc996b17ec7460d2c565 > 100644 > --- a/gcc/config/pa/pa.h > +++ b/gcc/config/pa/pa.h > @@ -1000,9 +1000,6 @@ do { > \ > done, UNKNOWN if none. */ > #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Specify the machine mode that pointers have. > After generation of rtl, the compiler makes no further distinction > between pointers and any other objects of this machine mode. */ > diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h > index > 115bb5b83a020cbfad42a449989d85ea7aaef680..835caf0333454723e6637e2491dae7e722b5bb87 > 100644 > --- a/gcc/config/pdp11/pdp11.h > +++ b/gcc/config/pdp11/pdp11.h > @@ -419,10 +419,6 @@ extern int may_call_alloca; > > #define MOVE_MAX 2 > > -/* Nonzero if access to memory by byte is slow and undesirable. - > -*/ > -#define SLOW_BYTE_ACCESS 0 > - > /* Do not break .stabs pseudos into continuations. */ > #define DBX_CONTIN_LENGTH 0 > > diff --git a/gcc/config/powerpcspe/powerpcspe.h > b/gcc/config/powerpcspe/powerpcspe.h > index > bc37c6f17e588aaa0b50271c0f0bdd06b0dc6002..18c8507c7d071e5011a3cc79c4501e59366bd58a > 100644 > --- a/gcc/config/powerpcspe/powerpcspe.h > +++ b/gcc/config/powerpcspe/powerpcspe.h > @@ -2084,11 +2084,6 @@ do { > \ > #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) > #define MAX_MOVE_MAX 8 > > -/* Nonzero if access to memory by bytes is no faster than for words. > - Also nonzero if doing byte operations (specifically shifts) in registers > - is undesirable. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD > will either zero-extend or sign-extend. The value of this macro should > be the code that says which one of the two operations is implicitly > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index > fe09e84e8953d24ba4d34217041cd798a0aa3057..19916e34eb4816713c41f15cd3794826a6416ee8 > 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -618,13 +618,6 @@ typedef struct { > #define MOVE_MAX UNITS_PER_WORD > #define MAX_MOVE_MAX 8 > > -/* The SPARC port says: > - Nonzero if access to memory by bytes is slow and undesirable. > - For RISC chips, it means that access to memory by bytes is no > - better than access by words when possible, so grab a whole word > - and maybe make use of that. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define SHIFT_COUNT_TRUNCATED 1 > > /* Specify the machine mode that pointers have. > diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h > index > e6b640986533251cbee504698794af1f2b89ed6d..237919d88ea9ba8fbcf10c3eee9b6fad2d3ff4cc > 100644 > --- a/gcc/config/rl78/rl78.h > +++ b/gcc/config/rl78/rl78.h > @@ -157,7 +157,6 @@ > #define HAVE_POST_INCREMENT 0 > > #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16) > -#define SLOW_BYTE_ACCESS 0 > > #define STORE_FLAG_VALUE 1 > #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND > diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h > index > 198110485c893251d90b33b1f780e6eff347dd60..ae6b38b16e26a53daef990b3399a3dc6cfb3fff2 > 100644 > --- a/gcc/config/rs6000/rs6000.h > +++ b/gcc/config/rs6000/rs6000.h > @@ -1980,11 +1980,6 @@ do { > \ > #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) > #define MAX_MOVE_MAX 8 > > -/* Nonzero if access to memory by bytes is no faster than for words. > - Also nonzero if doing byte operations (specifically shifts) in registers > - is undesirable. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD > will either zero-extend or sign-extend. The value of this macro should > be the code that says which one of the two operations is implicitly > diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h > index > 850033c1ee75e557d50788b4ce3cbc1efe82b2bc..e756fed56ba74908587cba5e66fd082f17eee5c7 > 100644 > --- a/gcc/config/rx/rx.h > +++ b/gcc/config/rx/rx.h > @@ -174,7 +174,6 @@ > #define HAVE_POST_INCREMENT 1 > > #define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2) > -#define SLOW_BYTE_ACCESS 1 > > #define STORE_FLAG_VALUE 1 > #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND > diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h > index > 15d33906023603e1a4d30a5e9697aa78a167534a..5836637e394e7c7a944003039d998e1c0babce9a > 100644 > --- a/gcc/config/s390/s390.h > +++ b/gcc/config/s390/s390.h > @@ -802,9 +802,6 @@ CUMULATIVE_ARGS; > is the default; other values are interpreted relative to that. */ > #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* An integer expression for the size in bits of the largest integer machine > mode that should actually be used. We allow pairs of registers. */ > #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) > diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h > index > f5d80da1451745e990461f5794c360878df62db2..91dd79f6e9c6187dec76819c2f5bf8e97e5f05d1 > 100644 > --- a/gcc/config/sh/sh.h > +++ b/gcc/config/sh/sh.h > @@ -1514,9 +1514,6 @@ extern bool current_function_interrupt; > /* Define if loading short immediate values into registers sign extends. */ > #define SHORT_IMMEDIATES_SIGN_EXTEND 1 > > -/* Nonzero if access to memory by bytes is no faster than for words. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Nonzero if the target supports dynamic shift instructions > like shad and shld. */ > #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) > diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h > index > a0b56126fd51fe4eedd6677cbac744fb0d443340..1022131705e9badbdaea13a3e366ca9ad2b1bf3d > 100644 > --- a/gcc/config/sparc/sparc.h > +++ b/gcc/config/sparc/sparc.h > @@ -1425,12 +1425,6 @@ do { > \ > done, UNKNOWN if none. */ > #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND > > -/* Nonzero if access to memory by bytes is slow and undesirable. > - For RISC chips, it means that access to memory by bytes is no > - better than access by words when possible, so grab a whole word > - and maybe make use of that. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Define this to be nonzero if shift instructions ignore all but the > low-order > few bits. */ > #define SHIFT_COUNT_TRUNCATED 1 > diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h > index > cf99b88b6acf29c438311db4e412aa7b35090e88..af38f618ac47dc1cee4dc1dc8521cfa3ef56b8da > 100644 > --- a/gcc/config/spu/spu.h > +++ b/gcc/config/spu/spu.h > @@ -373,8 +373,6 @@ do { > \ > > #define BRANCH_COST(speed_p, predictable_p) spu_branch_cost > > -#define SLOW_BYTE_ACCESS 0 > - > #define MOVE_RATIO(speed) ((speed)? 32 : 4) > > #define NO_FUNCTION_CSE 1 > diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h > index > 1d7045759c526ca8ee57a0b050769e73faa227db..bc1f23ea737779ecb6361354ae03e9176c698008 > 100644 > --- a/gcc/config/stormy16/stormy16.h > +++ b/gcc/config/stormy16/stormy16.h > @@ -320,8 +320,6 @@ enum reg_class > > #define BRANCH_COST(speed_p, predictable_p) 5 > > -#define SLOW_BYTE_ACCESS 0 > - > #define NO_FUNCTION_CSE 1 > > > diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h > index > ea3c1b308c723b2ce0ebeb669c2aee12c65f7829..cd5a13535f358092d4ce43917f41a607d271b15e > 100644 > --- a/gcc/config/tilegx/tilegx.h > +++ b/gcc/config/tilegx/tilegx.h > @@ -362,10 +362,6 @@ enum reg_class > (MODE) = DImode; \ > } > > -/* Define SLOW_BYTE_ACCESS to avoid making a QI or HI mode > - register. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define SHIFT_COUNT_TRUNCATED 0 > > #define SHORT_IMMEDIATES_SIGN_EXTEND 1 > diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h > index > 3aa6dc8cd677fba2ba677a64c2b97358562a1fc2..a980972609ff50418415bf3fcdb271a7d6ff2701 > 100644 > --- a/gcc/config/tilepro/tilepro.h > +++ b/gcc/config/tilepro/tilepro.h > @@ -321,10 +321,6 @@ enum reg_class > && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ > (MODE) = SImode; > > -/* Define SLOW_BYTE_ACCESS to avoid making a QI or HI mode > - register. */ > -#define SLOW_BYTE_ACCESS 1 > - > #define SHIFT_COUNT_TRUNCATED 1 > > #define SHORT_IMMEDIATES_SIGN_EXTEND 1 > diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h > index > 54dcc097bc485ada41991874d960c6665d20ca79..1c518415432c5065f096f8a977c7eb5af8bc950e > 100644 > --- a/gcc/config/v850/v850.h > +++ b/gcc/config/v850/v850.h > @@ -581,10 +581,6 @@ struct cum_arg { int nbytes; }; > #define CC_NO_CARRY CC_NO_OVERFLOW > #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN) > > -/* Nonzero if access to memory by bytes or half words is no faster > - than accessing full words. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* According expr.c, a value of around 6 should minimize code size, and > for the V850 series, that's our primary concern. */ > #define MOVE_RATIO(speed) 6 > diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h > index > 990140df869337c8e1e3f905c774fbf78a43ca1c..04da7a36172c9db15d7ab5d15fd7775b1afb3541 > 100644 > --- a/gcc/config/vax/vax.h > +++ b/gcc/config/vax/vax.h > @@ -434,9 +434,6 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES }; > #define MOVE_RATIO(speed) ((speed) ? 6 : 3) > #define CLEAR_RATIO(speed) ((speed) ? 6 : 2) > > -/* Nonzero if access to memory by bytes is slow and undesirable. */ > -#define SLOW_BYTE_ACCESS 0 > - > /* Define if shifts truncate the shift count > which implies one can omit a sign-extension or zero-extension > of a shift count. */ > diff --git a/gcc/config/visium/visium.h b/gcc/config/visium/visium.h > index > 85735953968d558a3d934bda0ef57cfab4f2f226..1525754cae341d48ec67465a64775c5f7516922f > 100644 > --- a/gcc/config/visium/visium.h > +++ b/gcc/config/visium/visium.h > @@ -1109,23 +1109,6 @@ do > \ > /* Override BRANCH_COST heuristics for complex logical ops. */ > #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 > > -/* `SLOW_BYTE_ACCESS' > - > - Define this macro as a C expression which is nonzero if accessing > - less than a word of memory (i.e. a `char' or a `short') is no > - faster than accessing a word of memory, i.e., if such access > - require more than one instruction or if there is no difference in > - cost between byte and (aligned) word loads. > - > - When this macro is not defined, the compiler will access a field by > - finding the smallest containing object; when it is defined, a > - fullword load will be used if alignment permits. Unless bytes > - accesses are faster than word accesses, using word accesses is > - preferable since it may eliminate subsequent memory access if > - subsequent accesses occur to other fields in the same word of the > - structure, but to different bytes. */ > -#define SLOW_BYTE_ACCESS 0 > - > /* `MOVE_RATIO (SPEED)` > > The threshold of number of scalar memory-to-memory move insns, > diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h > index > b4cf53708b3eb4a60846cf24003ae7b82f9aee99..3d2163e032e3ee0f73ca40e0f24e9b4dc424c137 > 100644 > --- a/gcc/config/xtensa/xtensa.h > +++ b/gcc/config/xtensa/xtensa.h > @@ -648,9 +648,6 @@ typedef struct xtensa_args > #define MOVE_MAX 4 > #define MAX_MOVE_MAX 4 > > -/* Prefer word-sized loads. */ > -#define SLOW_BYTE_ACCESS 1 > - > /* Shift instructions ignore all but the low-order few bits. */ > #define SHIFT_COUNT_TRUNCATED 1 > > diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi > index > 72606f53f1c991e0bfadcd5f23aaedaac5f0a8df..65f8425ccc1225a87bb2b1ac7e0acea33f48cda0 > 100644 > --- a/gcc/doc/tm.texi > +++ b/gcc/doc/tm.texi > @@ -6392,21 +6392,6 @@ Here are additional macros which do not specify > precise relative costs, > but only that certain actions are more expensive than GCC would > ordinarily expect. > > -@defmac SLOW_BYTE_ACCESS > -Define this macro as a C expression which is nonzero if accessing less > -than a word of memory (i.e.@: a @code{char} or a @code{short}) is no > -faster than accessing a word of memory, i.e., if such access > -require more than one instruction or if there is no difference in cost > -between byte and (aligned) word loads. > - > -When this macro is not defined, the compiler will access a field by > -finding the smallest containing object; when it is defined, a fullword > -load will be used if alignment permits. Unless bytes accesses are > -faster than word accesses, using word accesses is preferable since it > -may eliminate subsequent memory access if subsequent accesses occur to > -other fields in the same word of the structure, but to different bytes. > -@end defmac > - > @deftypefn {Target Hook} bool TARGET_SLOW_UNALIGNED_ACCESS (machine_mode > @var{mode}, unsigned int @var{align}) > This hook returns true if memory accesses described by the > @var{mode} and @var{alignment} parameters have a cost many times greater > diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in > index > e7d4ada290f49c5980eede3c6481fe04610f5d2c..92616339243563931176cf2fd5e09f748e024986 > 100644 > --- a/gcc/doc/tm.texi.in > +++ b/gcc/doc/tm.texi.in > @@ -4451,21 +4451,6 @@ Here are additional macros which do not specify > precise relative costs, > but only that certain actions are more expensive than GCC would > ordinarily expect. > > -@defmac SLOW_BYTE_ACCESS > -Define this macro as a C expression which is nonzero if accessing less > -than a word of memory (i.e.@: a @code{char} or a @code{short}) is no > -faster than accessing a word of memory, i.e., if such access > -require more than one instruction or if there is no difference in cost > -between byte and (aligned) word loads. > - > -When this macro is not defined, the compiler will access a field by > -finding the smallest containing object; when it is defined, a fullword > -load will be used if alignment permits. Unless bytes accesses are > -faster than word accesses, using word accesses is preferable since it > -may eliminate subsequent memory access if subsequent accesses occur to > -other fields in the same word of the structure, but to different bytes. > -@end defmac > - > @hook TARGET_SLOW_UNALIGNED_ACCESS > > @defmac MOVE_RATIO (@var{speed}) > diff --git a/gcc/dojump.c b/gcc/dojump.c > index > db8b278b982b6208196c8673b5571d91ee3d1658..5b1b5f747e236540a986317891810e24519aa4b7 > 100644 > --- a/gcc/dojump.c > +++ b/gcc/dojump.c > @@ -585,27 +585,6 @@ do_jump (tree exp, rtx_code_label *if_false_label, > } > } > > - /* If we are AND'ing with a small constant, do this comparison in the > - smallest type that fits. If the machine doesn't have comparisons > - that small, it will be converted back to the wider comparison. > - This helps if we are testing the sign bit of a narrower object. > - combine can't do this for us because it can't know whether a > - ZERO_EXTRACT or a compare in a smaller mode exists, but we do. */ > - > - if (! SLOW_BYTE_ACCESS > - && TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST > - && TYPE_PRECISION (TREE_TYPE (exp)) <= HOST_BITS_PER_WIDE_INT > - && (i = tree_floor_log2 (TREE_OPERAND (exp, 1))) >= 0 > - && int_mode_for_size (i + 1, 0).exists (&mode) > - && (type = lang_hooks.types.type_for_mode (mode, 1)) != 0 > - && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp)) > - && have_insn_for (COMPARE, TYPE_MODE (type))) > - { > - do_jump (fold_convert (type, exp), if_false_label, if_true_label, > - prob); > - break; > - } > - > if (TYPE_PRECISION (TREE_TYPE (exp)) > 1 > || TREE_CODE (TREE_OPERAND (exp, 1)) == INTEGER_CST) > goto normal; > diff --git a/gcc/stor-layout.c b/gcc/stor-layout.c > index > 7730ac33e4f62673f021ee95610c2e5e2e2843cb..c2116136fbfb61ea6eb5b10b774d99ac4179ce17 > 100644 > --- a/gcc/stor-layout.c > +++ b/gcc/stor-layout.c > @@ -2811,7 +2811,7 @@ bit_field_mode_iterator::prefer_smaller_modes () > { > return (m_volatilep > ? targetm.narrow_volatile_bitfield () > - : !SLOW_BYTE_ACCESS); > + : false); > } > > /* Find the best machine mode to use when referencing a bit field of length > @@ -2831,12 +2831,8 @@ bit_field_mode_iterator::prefer_smaller_modes () > > The underlying object is known to be aligned to a boundary of ALIGN bits. > > - If VOLATILEP is false and SLOW_BYTE_ACCESS is false, we return the > - smallest mode meeting these conditions. > - > - If VOLATILEP is false and SLOW_BYTE_ACCESS is true, we return the > - largest mode (but a mode no wider than UNITS_PER_WORD) that meets > - all the conditions. > + If VOLATILEP is false we return the largest mode (but a mode no wider > + than UNITS_PER_WORD) that meets all the conditions. > > If VOLATILEP is true the narrow_volatile_bitfields target hook is used to > decide which of the above modes should be used. */
