On 11/1/22 09:53, Tamar Christina wrote:
from the machine description.
+@cindex @code{tbranch@var{mode}4} instruction pattern @item
+@samp{tbranch@var{mode}4} Conditional branch instruction combined
+with a bit test-and-compare instruction. Operand 0 is a comparison
+operator. Operand 1 is the operand of the comparison. Operand 2 is
+the bit position of Operand 1 to test.
+Operand 3 is the @code{code_label} to jump to.
Should we refine/document the set of comparison operators allowed? Is
operand 1 an arbitrary RTL expression or more limited? I'm guessing its
relatively arbitrary given how you've massaged the existing branch-on-bit
patterns from the aarch backend.
It can be any expression in theory. However in practical terms we usually force
the values to registers before calling the expansion. My assumption is that
this
is for CSE purposes but that's only a guess.
Understood. And generally yes, forcing expressions into regs is good
for CSE.
Do we have enough information lying around from Ranger to avoid the need
to walk the def-use chain to discover that we're masking off all but one bit?
That's an interesting thought. I'll try to see if I can figure out how to query
Ranger here. It would be nice to do so here.
Reach out to Aldy, I suspect he can probably give you the necessary
pseudocode pretty quickly.
Jeff
