From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
* gcc.target/riscv/rvv/base/abi-3.c: Ditto.
* gcc.target/riscv/rvv/base/abi-4.c: Ditto.
* gcc.target/riscv/rvv/base/abi-5.c: Ditto.
* gcc.target/riscv/rvv/base/abi-6.c: Ditto.
* gcc.target/riscv/rvv/base/abi-7.c: Ditto.
* gcc.target/riscv/rvv/base/mov-1.c: Ditto.
* gcc.target/riscv/rvv/base/mov-10.c: Ditto.
* gcc.target/riscv/rvv/base/mov-11.c: Ditto.
* gcc.target/riscv/rvv/base/mov-12.c: Ditto.
* gcc.target/riscv/rvv/base/mov-13.c: Ditto.
* gcc.target/riscv/rvv/base/mov-2.c: Ditto.
* gcc.target/riscv/rvv/base/mov-3.c: Ditto.
* gcc.target/riscv/rvv/base/mov-4.c: Ditto.
* gcc.target/riscv/rvv/base/mov-5.c: Ditto.
* gcc.target/riscv/rvv/base/mov-6.c: Ditto.
* gcc.target/riscv/rvv/base/mov-7.c: Ditto.
* gcc.target/riscv/rvv/base/mov-8.c: Ditto.
* gcc.target/riscv/rvv/base/mov-9.c: Ditto.
* gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
* gcc.target/riscv/rvv/base/user-1.c: Ditto.
* gcc.target/riscv/rvv/base/user-2.c: Ditto.
* gcc.target/riscv/rvv/base/user-3.c: Ditto.
* gcc.target/riscv/rvv/base/user-4.c: Ditto.
* gcc.target/riscv/rvv/base/user-5.c: Ditto.
* gcc.target/riscv/rvv/base/user-6.c: Ditto.
* gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 8 ++++----
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 2 +-
27 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
index 92e61c255ac..9cd94c99308 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name
'__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;} /* { dg-error {unknown type name
'__rvv_bool32_t'} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
index b9adb3072f6..628a2753202 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
index 56a0ebed477..b4557aa6939 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
index af716094491..a58167f29ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;}
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
index e866c067e05..05b56e1cd28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name
'__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
index 407756de183..cc35ba1c6cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */
void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name
'__rvv_bool64_t'} } */
void foo1 () {__rvv_bool32_t t;}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e308f9..15e9c71f662 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa8297c30..e864554def6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb6b93..df5a36d0d68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40b62d..43a196a3e73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3bedb..23591aa8f7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd515747..90e67652056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db2735..dc3ca1f55cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b10b4..2d3744de66f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232ba867..13cc6699d6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73bb099..23b9da126de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0adfb..e87de71c677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05899d..1ea447b07bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c0f4d..7ed10bc5833 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include <riscv_vector.h>
@@ -7,12 +7,12 @@
/* Test tieable of RVV types with same LMUL. */
/*
** mov1:
+**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
**
vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]
+**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2
**
vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
**
vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
**
vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2
**
vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** ret
*/
@@ -28,10 +28,10 @@ void mov1 (int8_t *in, int8_t *out, int M)
/*
** mov2:
+**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
**
vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]
**
vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
**
vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
-**
addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1
**
vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)
** ret
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
index 3d81b179235..b271b0a1f3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
@@ -1,4 +1,4 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */
#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic'
option 'vector' needs 'V' extension enabled} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
index 00fb73f220f..63eea3fe901 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
index 92f4ee02d20..59ffe1062de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
index 3a425721863..86105e80d3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
index 76c5e607137..c854e3f8d92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
index de850e5e10d..f2b24733e57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
index 1d79b6b8eac..2c2c1ca3636 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */
+/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9170e..87698f306bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
#include <stddef.h>
#include <riscv_vector.h>
--
2.36.1
