On Thu, 27 Oct 2022 15:56:17 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
On 10/26/22 01:49, Sebastian Huber wrote:
The RV32A extension does not support 64-bit atomic operations. For RTEMS, use
a 32-bit gcov type for RV32.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gcov_type_size): New.
(TARGET_GCOV_TYPE_SIZE): Likewise.
* config/riscv/rtems.h (RISCV_GCOV_TYPE_SIZE): New.
Why make this specific to rtems? ISTM the logic behind this change
would apply independently of the os.
Looks like rv32gc is just broken here:
$ cat test.s
int func(int x) { return x + 1; }
$ gcc -march=rv32gc -O3 -fprofile-update=atomic -fprofile-arcs test.c -S -o-
func(int):
lui a4,%hi(__gcov0.func(int))
lw a5,%lo(__gcov0.func(int))(a4)
lw a2,%lo(__gcov0.func(int)+4)(a4)
addi a0,a0,1
addi a3,a5,1
sltu a5,a3,a5
add a5,a5,a2
sw a3,%lo(__gcov0.func(int))(a4)
sw a5,%lo(__gcov0.func(int)+4)(a4)
ret
_sub_I_00100_0:
lui a0,%hi(.LANCHOR0)
addi a0,a0,%lo(.LANCHOR0)
tail __gcov_init
_sub_D_00100_1:
tail __gcov_exit
__gcov0.func(int):
.zero 8
Those are not atomic...
On rv64 we got some amoadds, which are sane.
