On 9/29/22 01:44, Richard Biener wrote:
On Tue, Sep 27, 2022 at 9:54 PM Jeff Law <j...@ventanamicro.com> wrote:
This is another minor improvement to coremark. I suspect this only
improves code size as the load-immediate was likely issuing with the ret
statement on multi-issue machines.
Basically we're failing to utilize conditional equivalences during the
post-reload CSE pass. So if a particular block is only reached when a
certain condition holds (say for example a4 == 0) and the block has an
assignment like a4 = 0, we would fail to eliminate the unnecessary
assignment.
conditional equivalences on RTL - ick ;)
That was my first reaction as well.
I'm not familiar with RTL pattern matching so somebody else has to
comment on that, but
+ /* If this is not the first time through, then
+ verify the source and destination match. */
+ else if (dest == XEXP (cond, 0) && src == XEXP (cond, 1))
+ ;
shouldn't you restrict dest/src somehow? It might be a MEM?
The way you create the fake insn suggests only REG_P dest are OK
(not SUBREGs for example?)?
You're absolutely right, as is Richard S WRT unexpected sharing. I'll
adjust the patch appropriately.
Should you use rtx_equal_p (not using that possibly exempts MEM,
but being more explicit would be nice). Should you restrict this to
MODE_INT compares?
rtx_equal_p would be better, yes. I'll adjust that too.
This should work regardless of hte mode type though. The key is the
post-reload cse bits have to check that the pattern matches and that the
constraints are satisfied when a replacement is made. My only concern
would be MODE_CC stuff. I'll think a bit more about that case.
Jeff
