Hi Andrea,
> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm....@gcc.gnu.org> On Behalf Of Andrea
> Corallo via Gcc-patches
> Sent: Friday, August 12, 2022 4:42 PM
> To: Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org>
> Cc: Richard Earnshaw <richard.earns...@arm.com>; nd <n...@arm.com>
> Subject: [PATCH 12/15] arm: implement bti injection
>
> Hi all,
>
> this patch enables Branch Target Identification Armv8.1-M Mechanism
> [1].
>
> This is achieved by using the bti pass made common with Aarch64.
>
> The pass iterates through the instructions and adds the necessary BTI
> instructions at the beginning of every function and at every landing
> pads targeted by indirect jumps.
>
> Best Regards
>
> Andrea
>
> [1]
> <https://community.arm.com/developer/ip-
> products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-
> authentication-and-branch-target-identification-extension>
>
> gcc/ChangeLog
>
> 2022-04-07 Andrea Corallo <andrea.cora...@arm.com>
>
> * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
> * config/arm/arm-protos.h: Update.
> * config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
> (aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
> functions.
> * config/arm/arm.md (bti_nop): New insn.
> * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
> (aarch-bti-insert.o): New target.
> * config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
> * config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
> to verify arch compatibility.
> * config/arm/arm-passes.def: New file.
>
> gcc/testsuite/ChangeLog
>
> 2022-04-07 Andrea Corallo <andrea.cora...@arm.com>
>
> * gcc.target/arm/bti-1.c: New testcase.
> * gcc.target/arm/bti-2.c: Likewise.
diff --git a/gcc/config/arm/aarch-bti-insert.cc
b/gcc/config/arm/aarch-bti-insert.cc
index 2d1d2e334a9..8f045c247bf 100644
--- a/gcc/config/arm/aarch-bti-insert.cc
+++ b/gcc/config/arm/aarch-bti-insert.cc
@@ -41,6 +41,7 @@
#include "cfgrtl.h"
#include "tree-pass.h"
#include "cgraph.h"
+#include "diagnostic-core.h"
This change doesn't seem to match what's in the ChangeLog and doesn't make
sense to me.
@@ -32985,6 +32979,58 @@ arm_current_function_pac_enabled_p (void)
&& !crtl->is_leaf);
}
+/* Return TRUE if Branch Target Identification Mechanism is enabled. */
+bool
+aarch_bti_enabled (void)
+{
+ return aarch_enable_bti == 1;
+}
+
+/* Check if INSN is a BTI J insn. */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+ if (!insn || !INSN_P (insn))
+ return false;
+
+ rtx pat = PATTERN (insn);
+ return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPEC_BTI_NOP;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
The arm instructions are not PACIASP/PACIBSP.
This comment should be rewritten.
+bool
+aarch_pac_insn_p (rtx x)
+{
..........
+rtx
+aarch_gen_bti_c (void)
+{
+ return gen_bti_nop ();
+}
+
+rtx
+aarch_gen_bti_j (void)
+{
+ return gen_bti_nop ();
+}
+
A reader may be confused for why we have a bti_c and bti_j function that have
identical functionality.
Please add function comments explaining the situation.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 92269a7819a..90c8c1d66f5 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12913,6 +12913,13 @@
"aut\t%|ip, %|lr, %|sp"
[(set_attr "length" "4")])
+(define_insn "bti_nop"
+ [(unspec_volatile [(const_int 0)] UNSPEC_BTI_NOP)]
+ "arm_arch7 && arm_arch_cmse"
That seems like a copy-paste mistake. CMSE has nothing to do with this
functionality?
+ "bti"
+ [(set_attr "length" "4")
The length of instructions in the arm backend is 4 by default, this set_attr
can be omitted
+ (set_attr "type" "mov_reg")])
+
Probably better to use the "nop" attribute here?
Thanks,
Kyrill
