On Sat, 13 Aug 2022, mtsamis wrote:
> When using SWAR (SIMD in a register) techniques a comparison operation within
*within
> such a register can be made by using a combination of shifts, bitwise and and
> multiplication. If code using this scheme is vectorized then there is
> potential
> to replace all these operations with a single vector comparison, by
> reinterpreting
> the vector types to match the width of the SWAR register.
Hadn't it been for "all" modern processors these days having
SIMD instructions, adding general SWAR handling to the
vectorizer would be worth promoting to someones favorite
decision-maker. (This is a wonderful first step.)
Random typo spotted:
> +++ b/gcc/match.pd
> @@ -301,6 +301,63 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> (view_convert (bit_and:itype (view_convert @0)
> (ne @1 { build_zero_cst (type); })))))))
>
> +/* In SWAR (SIMD in a register) code a comparison of packed data can
> + be consturcted with a particular combination of shift, bitwise and,
*constructed
brgds, H-P
