On Thu, 28 Jul 2022, jiawei wrote:
> This patch adds the additional options on RISC-V target.
> "-fprefetch-loop-arrays" option needs enable prefetch instruction,
> for RISC-V that contained in "zicbop" extension.
> Use "-march" with "zicbop" will enable this feature.
OK.
Note -fprefetch-loop-arrays is just required to trigger an ICE,
do you see a diagnostic when prefetching is not supported? Maybe
simply adding -w is better then.
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
>
> ---
> gcc/testsuite/gcc.dg/pr106397.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
> index 2bc17f8cf80..19274fa8771 100644
> --- a/gcc/testsuite/gcc.dg/pr106397.c
> +++ b/gcc/testsuite/gcc.dg/pr106397.c
> @@ -1,6 +1,8 @@
> /* { dg-do compile } */
> /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param
> prefetch-latency=3 -fprefetch-loop-arrays" } */
> /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-*
> x86_64-*-* } && ia32 } } } */
> +/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } }
> */
> +/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } }
> */
>
> int
> bar (void)
>
--
Richard Biener <rguent...@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
HRB 36809 (AG Nuernberg)
