On Fri, Jul 15, 2022 at 3:28 PM Roger Sayle <ro...@nextmovesoftware.com> wrote:
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> This patch resolves PR target/106273 which is a wrong code regression
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> caused by the recent reorganization to split doubleword operations after
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> reload on x86.  For the failing test case, the constraints on the
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> andnti3_doubleword_bmi pattern allow reload to allocate the output and
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> operand in overlapping but non-identical registers, i.e.
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>
>
> (insn 45 44 66 2 (parallel [
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>             (set (reg/v:TI 5 di [orig:96 i ] [96])
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>                 (and:TI (not:TI (reg:TI 39 r11 [orig:83 _2 ] [83]))
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>                     (reg/v:TI 4 si [orig:100 i ] [100])))
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>             (clobber (reg:CC 17 flags))
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>         ]) "pr106273.c":13:5 562 {*andnti3_doubleword_bmi}
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>
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> where the output is in registers 5 and 6, and the second operand is
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> registers 4 and 5, which then leads to the incorrect split:
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>
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> (insn 113 44 114 2 (parallel [
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>             (set (reg:DI 5 di [orig:96 i ] [96])
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>                 (and:DI (not:DI (reg:DI 39 r11 [orig:83 _2 ] [83]))
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>                     (reg:DI 4 si [orig:100 i ] [100])))
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>             (clobber (reg:CC 17 flags))
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>         ]) "pr106273.c":13:5 566 {*andndi_1}
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>
>
> (insn 114 113 66 2 (parallel [
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>             (set (reg:DI 6 bp [ i+8 ])
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>                 (and:DI (not:DI (reg:DI 40 r12 [ _2+8 ]))
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>                     (reg:DI 5 di [ i+8 ])))
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>             (clobber (reg:CC 17 flags))
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>         ]) "pr106273.c":13:5 566 {*andndi_1}
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>
>
> [Notice that reg:DI 5 is set in the first instruction, but assumed
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> to have its original value in the second].  My first thought was
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> that this could be fixed by swapping the order of the split instructions
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> (which works in this case), but in the general case, it's impossible
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> to handle (set (reg:TI x) (op (reg:TI x+1) (reg:TI x-1)).  Hence for
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> correctness this pattern needs an earlyclobber "=&r", but we can also
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> allow cases where the output is the same as one of the operands (using
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> constraint "0").  The other binary logic operations (AND, IOR, XOR)
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> are unaffected as they constrain the output to match the first
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> operand, but BMI's andn is a three-operand instruction which can
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> lead to the overlapping cases described above.
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>
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> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
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> and make -k check, both with and without --target_board=unix{-m32} with
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> no new failures.  Ok for mainline?
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>
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> 2022-07-15  Roger Sayle  <ro...@nextmovesoftware.com>
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>
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> gcc/ChangeLog
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>         PR target/106273
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>         * config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Update the
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>         constraints to reflect the output is earlyclobber, unless it is
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>         the same register (pair) as one of the operands.
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>
>
> gcc/testsuite/ChangeLog
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>         PR target/106273
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>         * gcc.target/i386/pr106273.c: New test case.

OK with a small testcase adjustment.

Thanks,
Uros.

+int
+main (void)

If possible, please name this function "bar", the "main" function
assumes a runtime test.

+{
+  u8 x;
+  foo (5, &x);
+  if (x != 5)
+    __builtin_abort ();
+  return 0;
+}
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> Thanks again, and sorry for the inconvenience.
>
> Roger
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> --
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>

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