> gcc\ChangeLog:
It's minor but that should be gcc/ChangeLog rather than gcc\ChangeLog:
>
> gcc\testsuite\ChangeLog:
Same here.
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4999,10 +4999,14 @@ riscv_option_override (void)
> /* The presence of the M extension implies that division instructions
> are present, so include them unless explicitly disabled. */
> if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
> - target_flags |= MASK_DIV;
> + if(!TARGET_ZMMUL)
> + target_flags |= MASK_DIV;
> else if (!TARGET_MUL && TARGET_DIV)
> error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
> -
> +
> + if(TARGET_ZMMUL && TARGET_MUL)
Should be + if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV)
Otherwise that treat rv32im_zmmul becomes an invalid arch string, but
actually that's a valid combination.
> + warning (0, "%<-mdiv%> cannot use when the %<ZMMUL%> extension is
> present");
Google suggest that : "%<-mdiv%> cannot be used when %<ZMMUL%>
extension is present" :P
> +
> /* Likewise floating-point division and square root. */
> if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
> target_flags |= MASK_FDIV;
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 308b64dd30d..d4e171464ea 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -763,7 +763,7 @@
> [(set (match_operand:SI 0 "register_operand" "=r")
> (mult:SI (match_operand:SI 1 "register_operand" " r")
> (match_operand:SI 2 "register_operand" " r")))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -772,7 +772,7 @@
> [(set (match_operand:DI 0 "register_operand" "=r")
> (mult:DI (match_operand:DI 1 "register_operand" " r")
> (match_operand:DI 2 "register_operand" " r")))]
> - "TARGET_MUL && TARGET_64BIT"
> + "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT"
> "mul\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -782,7 +782,7 @@
> (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> (match_operand:GPR 2 "register_operand" " r")))
> (label_ref (match_operand 3 "" ""))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> {
> if (TARGET_64BIT && <MODE>mode == SImode)
> {
> @@ -827,7 +827,7 @@
> (mult:GPR (match_operand:GPR 1 "register_operand" " r")
> (match_operand:GPR 2 "register_operand" " r")))
> (label_ref (match_operand 3 "" ""))]
> - "TARGET_MUL"
> + "TARGET_ZMMUL || TARGET_MUL"
> {
> if (TARGET_64BIT && <MODE>mode == SImode)
> {
> @@ -873,7 +873,7 @@
> (sign_extend:DI
> (mult:SI (match_operand:SI 1 "register_operand" " r")
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulw\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -884,7 +884,7 @@
> (match_operator:SI 3 "subreg_lowpart_operator"
> [(mult:DI (match_operand:DI 1 "register_operand" " r")
> (match_operand:DI 2 "register_operand" " r"))])))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulw\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -902,7 +902,7 @@
> [(set (match_operand:TI 0 "register_operand")
> (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
> (any_extend:TI (match_operand:DI 2 "register_operand"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> {
> rtx low = gen_reg_rtx (DImode);
> emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> @@ -924,7 +924,7 @@
> (any_extend:TI
> (match_operand:DI 2 "register_operand" " r")))
> (const_int 64))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulh<u>\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -933,7 +933,7 @@
> [(set (match_operand:TI 0 "register_operand")
> (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand"))
> (sign_extend:TI (match_operand:DI 2 "register_operand"))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> {
> rtx low = gen_reg_rtx (DImode);
> emit_insn (gen_muldi3 (low, operands[1], operands[2]));
> @@ -955,7 +955,7 @@
> (sign_extend:TI
> (match_operand:DI 2 "register_operand" " r")))
> (const_int 64))))]
> - "TARGET_MUL && TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT"
> "mulhsu\t%0,%2,%1"
> [(set_attr "type" "imul")
> (set_attr "mode" "DI")])
> @@ -966,7 +966,7 @@
> (match_operand:SI 1 "register_operand" " r"))
> (any_extend:DI
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> {
> rtx temp = gen_reg_rtx (SImode);
> emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> @@ -985,7 +985,7 @@
> (any_extend:DI
> (match_operand:SI 2 "register_operand" " r")))
> (const_int 32))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> "mulh<u>\t%0,%1,%2"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> @@ -997,7 +997,7 @@
> (match_operand:SI 1 "register_operand" " r"))
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" " r"))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> {
> rtx temp = gen_reg_rtx (SImode);
> emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
> @@ -1016,7 +1016,7 @@
> (sign_extend:DI
> (match_operand:SI 2 "register_operand" " r")))
> (const_int 32))))]
> - "TARGET_MUL && !TARGET_64BIT"
> + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT"
> "mulhsu\t%0,%2,%1"
> [(set_attr "type" "imul")
> (set_attr "mode" "SI")])
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 9e9fe6d8ccd..f93521c1e70 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -212,6 +212,9 @@ int riscv_zvl_flags
> TargetVariable
> int riscv_zicmo_subext
>
> +TargetVariable
> +int riscv_zm_subext
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-1.c
> b/gcc/testsuite/gcc.target/riscv/zmmul-1.c
> new file mode 100644
> index 00000000000..cdae2cb55df
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zmmul-1.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64" } */
> +int foo1(int a, int b)
> +{
> + return a*b;
> +}
> +
> +int foo2(int a, int b)
> +{
> + return a/b;
> +}
> +
> +int foo3(int a, int b)
> +{
> + return a%b;
> +}
> +
> +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */
> +/* { dg-final { scan-assembler-not "div\t" } } */
> +/* { dg-final { scan-assembler-not "rem\t" } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-2.c
> b/gcc/testsuite/gcc.target/riscv/zmmul-2.c
> new file mode 100644
> index 00000000000..dc6829da92e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zmmul-2.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32iafdc_zmmul -mabi=ilp32" } */
> +int foo1(int a, int b)
> +{
> + return a*b;
> +}
> +
> +int foo2(int a, int b)
> +{
> + return a/b;
> +}
> +
> +int foo3(int a, int b)
> +{
> + return a%b;
> +}
> +
> +/* { dg-final { scan-assembler-times "mul\t" 1 } } */
> +/* { dg-final { scan-assembler-not "div\t" } } */
> +/* { dg-final { scan-assembler-not "rem\t" } } */
> \ No newline at end of file
> --
> 2.31.1.windows.1
>
