On Mon, Jun 13, 2022 at 8:54 PM Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp> wrote: > > When spilled DFmode registers are reloaded in, once loaded into a pair of > SImode regs and then copied from that regs. Such unwanted reg-reg moves > seems not to be eliminated at the "cprop_hardreg" stage, despite no problem > in output reloads. > > Luckily it is easy to resolve such inefficiencies, with the use of peephole2 > pattern. > > gcc/ChangeLog: > > * config/xtensa/predicates.md (reload_operand): > New predicate. > * config/xtensa/xtensa.md: New peephole2 pattern. > --- > gcc/config/xtensa/predicates.md | 13 +++++++++++++ > gcc/config/xtensa/xtensa.md | 31 +++++++++++++++++++++++++++++++ > 2 files changed, 44 insertions(+)
Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max
