From: Christoph Müllner <christoph.muell...@vrull.eu>
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-thead-c906.c: New test.
Changes since v1:
* Adding test case
* Reword commit message
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
gcc/config/riscv/riscv-cores.def | 2 ++
.../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 60bcadbb034..dd97ece376f 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
+RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906")
+
#undef RISCV_CORE
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
new file mode 100644
index 00000000000..f579e7e2215
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
+/* T-Head XuanTie C906 => rv64imafdc */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
--
2.35.3
