On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner
<christoph.muell...@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muell...@vrull.eu>
>
> This adds Allwinner's D1 to the list of known cores.
> The Allwinner includes a single-core XuanTie C906 and is available
> for quite some time. Note, that the tuning struct for the C906
> is already part of GCC.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1".
>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> ---
> gcc/config/riscv/riscv-cores.def | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> index 60bcadbb034..dd97ece376f 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc",
> "sifive-7-series")
> RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
> RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
>
> +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906")
I just realized that this lacks a test case (other -mcpu=... entries have one).
And the core string is wrong (s/thead-c906/allwinner-d1).
I will send a v2.
> +
> #undef RISCV_CORE
> --
> 2.35.3
>
