Hi, This patch is same with nearly: https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595378.html
The concept of this patch is similar with the patches which is attached in PR63281. e.g. https://gcc.gnu.org/bugzilla/attachment.cgi?id=42186 I had a test for perlbench from SPEC2017. As expected, on -O2 for P9, there is ~2% performance improvement with this patch. This patch reduces the threshold of instruction number for storing constant to pool and update cost for constant and mem accessing. And then if building the constant needs more than 2 instructions (or more than 1 instruction on P10), then prefer to load it from constant pool. Bootstrap and regtest pass on ppc64le and ppc64. Is this ok for trunk? Thanks for comments and sugguestions. BR, Jiufu PR target/63281 gcc/ChangeLog: 2022-06-14 Jiufu Guo <guoji...@linux.ibm.com> Alan Modra <amo...@gmail.com> * config/rs6000/rs6000.cc (rs6000_cannot_force_const_mem): Exclude rtx with code 'HIGH'. (rs6000_emit_move): Update threshold of const insn. (rs6000_rtx_costs): Update cost of constant and mem. gcc/testsuite/ChangeLog: 2022-06-14 Jiufu Guo <guoji...@linux.ibm.com> Alan Modra <amo...@gmail.com> * gcc.target/powerpc/medium_offset.c: Update. * gcc.target/powerpc/pr93012.c: Update. * gcc.target/powerpc/pr63281.c: New test. --- gcc/config/rs6000/rs6000.cc | 23 +++++++++++++++---- .../gcc.target/powerpc/medium_offset.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr63281.c | 11 +++++++++ gcc/testsuite/gcc.target/powerpc/pr93012.c | 2 +- 4 files changed, 31 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr63281.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index cd291f93019..90c91a8e1ea 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -9706,8 +9706,9 @@ rs6000_init_stack_protect_guard (void) static bool rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) { - if (GET_CODE (x) == HIGH - && GET_CODE (XEXP (x, 0)) == UNSPEC) + /* Exclude CONSTANT HIGH part. e.g. + (high:DI (symbol_ref:DI ("var") [flags 0xc0] <var_decl>)). */ + if (GET_CODE (x) == HIGH) return true; /* A TLS symbol in the TOC cannot contain a sum. */ @@ -11139,7 +11140,7 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode) && FP_REGNO_P (REGNO (operands[0]))) || !CONST_INT_P (operands[1]) || (num_insns_constant (operands[1], mode) - > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2))) + > (TARGET_PREFIXED ? 1 : 2))) && !toc_relative_expr_p (operands[1], false, NULL, NULL) && (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p () @@ -22101,6 +22102,14 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, case CONST_DOUBLE: case CONST_WIDE_INT: + /* It may needs a few insns for const to SET. -1 for outer SET code. */ + if (outer_code == SET) + { + *total = COSTS_N_INSNS (num_insns_constant (x, mode)) - 1; + return true; + } + /* FALLTHRU */ + case CONST: case HIGH: case SYMBOL_REF: @@ -22110,8 +22119,12 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, case MEM: /* When optimizing for size, MEM should be slightly more expensive than generating address, e.g., (plus (reg) (const)). - L1 cache latency is about two instructions. */ - *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); + L1 cache latency is about two instructions. + For prefixed load (pld), we would set it slightly faster than + than two instructions. */ + *total = !speed + ? COSTS_N_INSNS (1) + 1 + : TARGET_PREFIXED ? COSTS_N_INSNS (2) - 1 : COSTS_N_INSNS (2); if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x))) *total += COSTS_N_INSNS (100); return true; diff --git a/gcc/testsuite/gcc.target/powerpc/medium_offset.c b/gcc/testsuite/gcc.target/powerpc/medium_offset.c index f29eba08c38..4889e8fa8ec 100644 --- a/gcc/testsuite/gcc.target/powerpc/medium_offset.c +++ b/gcc/testsuite/gcc.target/powerpc/medium_offset.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ /* { dg-options "-O" } */ -/* { dg-final { scan-assembler-not "\\+4611686018427387904" } } */ +/* { dg-final { scan-assembler-times {\msldi|pld\M} 1 } } */ static int x; diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c new file mode 100644 index 00000000000..469a8f64400 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -0,0 +1,11 @@ +/* PR target/63281 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -std=c99" } */ + +void +foo (unsigned long long *a) +{ + *a = 0x020805006106003; +} + +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr93012.c b/gcc/testsuite/gcc.target/powerpc/pr93012.c index 4f764d0576f..5afb4f79c45 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr93012.c +++ b/gcc/testsuite/gcc.target/powerpc/pr93012.c @@ -10,4 +10,4 @@ unsigned long long mskh1() { return 0xffff9234ffff9234ULL; } unsigned long long mskl1() { return 0x2bcdffff2bcdffffULL; } unsigned long long mskse() { return 0xffff1234ffff1234ULL; } -/* { dg-final { scan-assembler-times {\mrldimi\M} 7 } } */ +/* { dg-final { scan-assembler-times {\mrldimi|ld|pld\M} 7 } } */ -- 2.25.1
