On Mon, Jun 13, 2022 at 9:39 AM Takayuki 'January June' Suwa <jjsuwa_sys3...@yahoo.co.jp> wrote: > > On 2022/06/13 12:49, Max Filippov wrote: > > Hi Suwa-san, > hi! > > > This change produces a bunch of regression test failures in big-endian > > configuration: > bad news X( > that point is what i was a little worried about... > > > E.g. for the test gcc.c-torture/execute/struct-ini-2.c > > the following assembly code is generated now: > > and the following code was generated before this change: > - .literal .LC1, -4096 > - l32r a10, .LC1 > - and a10, a8, a10 > + extui a10, a8, 16, 4 // wrong! must be 12, 4 > + slli a10, a10, 12 > and of course, '(zero_extract)' is endianness-sensitive. > (ref. 14.11 Bit-Fields, gcc-internals) > > the all patches that i previouly posted do not match or emit > '(zero_extract)', except for this case. > > === > This patch offers several insn-and-split patterns for bitwise AND with > register and constant that can be represented as: > > i. 1's least significant N bits and the others 0's (17 <= N <= 31) > ii. 1's most significant N bits and the others 0's (12 <= N <= 31) > iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a > "MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30) > > And also offers shortcuts for conditional branch if each of the abovementioned > operations is (not) equal to zero. > > gcc/ChangeLog: > > * config/xtensa/predicates.md (shifted_mask_operand): > New predicate. > * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): > New insn-and-split pattern. > (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, > *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, > *masktrue_const_shifted_mask): Ditto. > --- > gcc/config/xtensa/predicates.md | 10 ++ > gcc/config/xtensa/xtensa.md | 179 ++++++++++++++++++++++++++++++++ > 2 files changed, 189 insertions(+)
Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max
