FP_ISA3 is exactly the same as SFDF, just a less obvious name. So,
let's delete it.
Tested, committed, the works.
Segher
2022-06-09 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.md (FP_ISA3): Delete.
(float<QHI:mode><FP_ISA3:mode>2): Rename to...
(float<QHI:mode><SFDF:mode>2): ... this. Adjust.
(*float<QHI:mode><FP_ISA3:mode>2_internal): Rename to...
(*float<QHI:mode><SFDF:mode>2_internal): ... this. Adjust.
(floatuns<QHI:mode><FP_ISA3:mode>2): Rename to...
(floatuns<QHI:mode><SFDF:mode>2): ... this. Adjust.
(*floatuns<QHI:mode><FP_ISA3:mode>2_internal): Rename to...
(*floatuns<QHI:mode><SFDF:mode>2_internal): ... this. Adjust.
---
gcc/config/rs6000/rs6000.md | 31 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1c125f07e895..c55ee7e171a3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -619,9 +619,6 @@ (define_mode_iterator FLOAT128 [(KF "TARGET_FLOAT128_TYPE")
(define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
-; Iterator for ISA 3.0 supported floating point types
-(define_mode_iterator FP_ISA3 [SF DF])
-
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -6012,9 +6009,9 @@ (define_insn_and_split "*floatunssidf2_internal"
;; the vector registers, rather then loading up a GPR, doing a sign/zero
;; extension and then a direct move.
-(define_expand "float<QHI:mode><FP_ISA3:mode>2"
- [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
- (float:FP_ISA3
+(define_expand "float<QHI:mode><SFDF:mode>2"
+ [(parallel [(set (match_operand:SFDF 0 "vsx_register_operand")
+ (float:SFDF
(match_operand:QHI 1 "input_operand")))
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))
@@ -6025,9 +6022,9 @@ (define_expand "float<QHI:mode><FP_ISA3:mode>2"
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
})
-(define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
- [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
- (float:FP_ISA3
+(define_insn_and_split "*float<QHI:mode><SFDF:mode>2_internal"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa,wa,wa")
+ (float:SFDF
(match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
(clobber (match_scratch:DI 2 "=v,wa,v"))
(clobber (match_scratch:DI 3 "=X,r,X"))
@@ -6061,14 +6058,14 @@ (define_insn_and_split
"*float<QHI:mode><FP_ISA3:mode>2_internal"
emit_insn (gen_extend<QHI:mode>di2 (di, tmp));
}
- emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
+ emit_insn (gen_floatdi<SFDF:mode>2 (result, di));
DONE;
}
[(set_attr "isa" "p9v,*,p9v")])
-(define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
- [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
- (unsigned_float:FP_ISA3
+(define_expand "floatuns<QHI:mode><SFDF:mode>2"
+ [(parallel [(set (match_operand:SFDF 0 "vsx_register_operand")
+ (unsigned_float:SFDF
(match_operand:QHI 1 "input_operand")))
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))])]
@@ -6078,9 +6075,9 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
})
-(define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
- [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=wa,wa,wa")
- (unsigned_float:FP_ISA3
+(define_insn_and_split "*floatuns<QHI:mode><SFDF:mode>2_internal"
+ [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa,wa,wa")
+ (unsigned_float:SFDF
(match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
(clobber (match_scratch:DI 2 "=v,wa,wa"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
@@ -6107,7 +6104,7 @@ (define_insn_and_split
"*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
}
}
- emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
+ emit_insn (gen_floatdi<SFDF:mode>2 (result, di));
DONE;
}
[(set_attr "isa" "p9v,*,p9v")])
--
1.8.3.1
