On Wed, May 18, 2022 at 9:08 AM Prathamesh Kulkarni via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi, > The attached patch adds another parameter machine_mode op_mode to > vec_perm_const > hook to specify mode of input operands. The motivation for doing this > is PR96463, > where we create vec_perm_expr of the form: > lhs = vec_perm_expr<rhs, mask> > where lhs and rhs have different vector types but same element type > (lhs is SVE and rhs is corresponding advsimd vector). > > It seems the following targets were affected: aarch64, i386, arm, ia64, > mips, rs6000, s390, sparc, gcn. > > Bootstrapped+tested on x86_64-linux-gnu, aarch64-linux-gnu. > For other targets, I did make all-gcc stage1, which seems to build OK.
So it would also allow to express extract even/odd and interleave operations with a VEC_PERM. The interleave currently has the issue that we have to artificially widen the inputs with "dont-care" elements. The lo/high variants can already do with a bitfield-ref or vector-of-vector CTOR. Richard. > > Thanks, > Prathamesh
