This is a revised version of my i386 backend patch to avoid andn with -Oz,
when an explicit not;and (or not;test) would be (one byte) shorter.
https://gcc.gnu.org/pipermail/gcc-patches/2022-April/593168.html
This revision incorporates Michael Matz's feedback/suggestions with
explicit checks for LEGACY_INT_REG_P and REX_INT_REG_P.
This patch has been tested against gcc13 trunk on x86_64-pc-linux-gnu
with make bootstrap and make -k check, both with and without
--target_board=unix{-m32}, with no new failures. Ok for mainline?
2022-05-17 Roger Sayle <ro...@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386.md (define_split): Split *andsi_1 and
*andn_si_ccno after reload with -Oz.
gcc/testsuite/ChangeLog
* gcc.target/i386/bmi-and-3.c: New test case.
Thanks in advance,
Roger
--
> -----Original Message-----
> From: Michael Matz <m...@suse.de>
> Sent: 13 April 2022 14:11
> To: Roger Sayle <ro...@nextmovesoftware.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [x86 PATCH] Avoid andn and generate shorter not;and with -Oz.
>
> Hello,
>
> On Wed, 13 Apr 2022, Roger Sayle wrote:
>
> > The x86 instruction encoding for SImode andn is longer than the
> > equivalent notl/andl sequence when the source for the not operand is
> > the same register as the destination.
>
> _And_ when no REX prefixes are necessary for the notl,andn, which they are
if
> the respective registers are %r8 or beyond. As you seem to be fine with
saving
> just a byte you ought to test that as well to not waste one again :-)
>
>
> Ciao,
> Michael.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f9c06ff..33473c6 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10401,6 +10401,40 @@
[(set_attr "type" "bitmanip")
(set_attr "btver2_decode" "direct, double")
(set_attr "mode" "<MODE>")])
+
+;; Split *andnsi_1 after reload with -Oz when not;and is shorter.
+(define_split
+ [(set (match_operand:SI 0 "register_operand")
+ (and:SI (not:SI (match_operand:SI 1 "register_operand"))
+ (match_operand:SI 2 "nonimmediate_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "reload_completed
+ && optimize_insn_for_size_p () && optimize_size > 1
+ && REGNO (operands[0]) == REGNO (operands[1])
+ && LEGACY_INT_REG_P (operands[0])
+ && !REX_INT_REG_P (operands[2])
+ && !reg_overlap_mentioned_p (operands[0], operands[2])"
+ [(set (match_dup 0) (not:SI (match_dup 1)))
+ (parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC FLAGS_REG))])])
+
+;; Split *andn_si_ccno with -Oz when not;test is shorter.
+(define_split
+ [(set (match_operand 0 "flags_reg_operand")
+ (match_operator 1 "compare_operator"
+ [(and:SI (not:SI (match_operand:SI 2 "general_reg_operand"))
+ (match_operand:SI 3 "nonimmediate_operand"))
+ (const_int 0)]))
+ (clobber (match_dup 2))]
+ "reload_completed
+ && optimize_insn_for_size_p () && optimize_size > 1
+ && LEGACY_INT_REG_P (operands[2])
+ && !REX_INT_REG_P (operands[3])
+ && !reg_overlap_mentioned_p (operands[2], operands[3])"
+ [(set (match_dup 2) (not:SI (match_dup 2)))
+ (set (match_dup 0) (match_op_dup 1
+ [(and:SI (match_dup 3) (match_dup 2))
+ (const_int 0)]))])
;; Logical inclusive and exclusive OR instructions
diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-3.c
b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c
new file mode 100644
index 0000000..16993a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-Oz -mbmi" } */
+int m;
+
+int foo(int x, int y)
+{
+ return (x & ~y) != 0;
+}
+
+int bar(int x)
+{
+ return (~x & m) != 0;
+}
+/* { dg-final { scan-assembler-not "andn\[ \\t\]+" } } */
+
