On Tue, May 17, 2022 at 5:06 AM liuhongt <hongtao....@intel.com> wrote:
>
> backend has
>
> 16550(define_insn "*bmi2_bzhi_<mode>3_2"
> 16551 [(set (match_operand:SWI48 0 "register_operand" "=r")
> 16552 (and:SWI48
> 16553 (plus:SWI48
> 16554 (ashift:SWI48 (const_int 1)
> 16555 (match_operand:QI 2 "register_operand" "r"))
> 16556 (const_int -1))
> 16557 (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
> 16558 (clobber (reg:CC FLAGS_REG))]
> 16559 "TARGET_BMI2"
> 16560 "bzhi\t{%<k>2, %1, %0|%0, %1, %<k>2}"
> 16561 [(set_attr "type" "bitmanip")
> 16562 (set_attr "prefix" "vex")
> 16563 (set_attr "mode" "<MODE>")])
>
> But there's extra zero_extend in pattern match.
>
> 424Failed to match this instruction:
> 425(parallel [
> 426 (set (reg:DI 90)
> 427 (zero_extend:DI (and:SI (plus:SI (ashift:SI (const_int 1 [0x1])
> 428 (subreg:QI (reg:SI 98) 0))
> 429 (const_int -1 [0xffffffffffffffff]))
> 430 (subreg:SI (reg:DI 95) 0))))
> 431 (clobber (reg:CC 17 flags))
> 432 ])
>
> Add new define_insn for it.
>
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}..
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/104375
> * config/i386/i386.md (*bmi2_bzhi_zero_extendsidi_4): New
> define_insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr104375.c: New test.
OK with a nit below.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.md | 16 ++++++++++++++++
> gcc/testsuite/gcc.target/i386/pr104375.c | 9 +++++++++
> 2 files changed, 25 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr104375.c
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index f9c06ff302a..ec7bdd04947 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -16636,6 +16636,22 @@ (define_insn "*bmi2_bzhi_<mode>3_3"
> (set_attr "prefix" "vex")
> (set_attr "mode" "<MODE>")])
>
> +(define_insn "*bmi2_bzhi_zero_extendsidi_4"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (zero_extend:DI
> + (and:SI
> + (plus:SI
> + (ashift:SI (const_int 1)
> + (match_operand:QI 2 "register_operand" "r"))
> + (const_int -1))
> + (match_operand:SI 1 "nonimmediate_operand" "rm"))))
> + (clobber (reg:CC FLAGS_REG))]
> + "TARGET_BMI2 && TARGET_64BIT"
Please put TARGET_64BIT first here.
> + "bzhi\t{%q2, %q1, %q0|%q0, %q1, %q2}"
> + [(set_attr "type" "bitmanip")
> + (set_attr "prefix" "vex")
> + (set_attr "mode" "DI")])
> +
> (define_insn "bmi2_pdep_<mode>3"
> [(set (match_operand:SWI48 0 "register_operand" "=r")
> (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
> diff --git a/gcc/testsuite/gcc.target/i386/pr104375.c
> b/gcc/testsuite/gcc.target/i386/pr104375.c
> new file mode 100644
> index 00000000000..5c9f511da5c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104375.c
> @@ -0,0 +1,9 @@
> +#/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mbmi2 -O2" } */
> +/* { dg-final { scan-assembler-times {(?n)shrx[\t ]+} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)bzhi[\t ]+} 1 } } */
> +
> +unsigned long long bextr_u64(unsigned long long w, unsigned off, unsigned
> int len)
> +{
> + return (w >> off) & ((1U << len) - 1U);
> +}
> --
> 2.18.1
>
