The <Ff> mode iterator can just use "d" always.
2022-05-11 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.md: Use d instead of <Ff>.
---
gcc/config/rs6000/rs6000.md | 117 +++++++++++++++++++++-----------------------
1 file changed, 57 insertions(+), 60 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 64049a6e521c..0100d67e9217 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -622,9 +622,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P
(KFmode)")
; Iterator for ISA 3.0 supported floating point types
(define_mode_iterator FP_ISA3 [SF DF])
-; SF/DF constraint for arithmetic on traditional floating point registers
-(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
-
; SF/DF constraint for arithmetic on VSX registers using instructions added in
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
@@ -4871,8 +4868,8 @@ (define_expand "abs<mode>2"
"")
(define_insn "*abs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
"TARGET_HARD_FLOAT"
"@
fabs %0,%1
@@ -4880,10 +4877,10 @@ (define_insn "*abs<mode>2_fpr"
[(set_attr "type" "fpsimple")])
(define_insn "*nabs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
(neg:SFDF
(abs:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))))]
"TARGET_HARD_FLOAT"
"@
fnabs %0,%1
@@ -4897,8 +4894,8 @@ (define_expand "neg<mode>2"
"")
(define_insn "*neg<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
"TARGET_HARD_FLOAT"
"@
fneg %0,%1
@@ -4913,9 +4910,9 @@ (define_expand "add<mode>3"
"")
(define_insn "*add<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
fadd<s> %0,%1,%2
@@ -4931,9 +4928,9 @@ (define_expand "sub<mode>3"
"")
(define_insn "*sub<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
fsub<s> %0,%1,%2
@@ -4949,9 +4946,9 @@ (define_expand "mul<mode>3"
"")
(define_insn "*mul<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
fmul<s> %0,%1,%2
@@ -4975,9 +4972,9 @@ (define_expand "div<mode>3"
})
(define_insn "*div<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
fdiv<s> %0,%1,%2
@@ -4986,8 +4983,8 @@ (define_insn "*div<mode>3_fpr"
(set_attr "isa" "*,<Fisa>")])
(define_insn "*sqrt<mode>2_internal"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@
fsqrt<s> %0,%1
@@ -5014,8 +5011,8 @@ (define_expand "sqrt<mode>2"
;; Floating point reciprocal approximation
(define_insn "fre<sd>"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRES))]
"TARGET_<FFRE>"
"@
@@ -5061,8 +5058,8 @@ (define_expand "remainder<mode>3"
})
(define_insn "*rsqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@
@@ -5074,8 +5071,8 @@ (define_insn "*rsqrt<mode>2"
;; Floating point comparisons
(define_insn "*cmp<mode>_fpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
- (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
fcmpu %0,%1,%2
@@ -5277,9 +5274,9 @@ (define_expand "copysign<mode>3"
;; Use an unspec rather providing an if-then-else in RTL, to prevent the
;; compiler from optimizing -0.0
(define_insn "copysign<mode>3_fcpsgn"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,<Fv>")]
UNSPEC_COPYSIGN))]
"TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
@@ -6205,7 +6202,7 @@ (define_expand "fix_trunc<mode>di2"
(define_insn "*fix_trunc<mode>di2_fctidz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
- (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"@
fctidz %0,%1
@@ -6324,7 +6321,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
(define_insn "fixuns_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
- (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
"@
fctiduz %0,%1
@@ -6474,7 +6471,7 @@ (define_expand "rs6000_set_fpscr_drn"
(define_insn "fctiwz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(unspec:DI [(fix:SI
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
UNSPEC_FCTIWZ))]
"TARGET_HARD_FLOAT"
"@
@@ -6485,7 +6482,7 @@ (define_insn "fctiwz_<mode>"
(define_insn "fctiwuz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(unspec:DI [(unsigned_fix:SI
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>"))]
UNSPEC_FCTIWUZ))]
"TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
"@
@@ -6588,8 +6585,8 @@ (define_insn "lrint<mode>di2"
[(set_attr "type" "fp")])
(define_insn "btrunc<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
UNSPEC_FRIZ))]
"TARGET_HARD_FLOAT && TARGET_FPRND"
"@
@@ -6598,8 +6595,8 @@ (define_insn "btrunc<mode>2"
[(set_attr "type" "fp")])
(define_insn "ceil<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
UNSPEC_FRIP))]
"TARGET_HARD_FLOAT && TARGET_FPRND"
"@
@@ -6608,8 +6605,8 @@ (define_insn "ceil<mode>2"
[(set_attr "type" "fp")])
(define_insn "floor<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<Fv>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,<Fv>")]
UNSPEC_FRIM))]
"TARGET_HARD_FLOAT && TARGET_FPRND"
"@
@@ -10152,7 +10149,7 @@ (define_insn "*movqi_update3"
(set_attr "indexed" "yes,no")])
(define_insn "*mov<SFDF:mode>_update1"
- [(set (match_operand:SFDF 3 "gpc_reg_operand" "=<SFDF:Ff>,<SFDF:Ff>")
+ [(set (match_operand:SFDF 3 "gpc_reg_operand" "=d,d")
(mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
(match_operand:P 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
@@ -10171,7 +10168,7 @@ (define_insn "*mov<SFDF:mode>_update1"
(define_insn "*mov<SFDF:mode>_update2"
[(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
(match_operand:P 2 "reg_or_short_operand" "r,I")))
- (match_operand:SFDF 3 "gpc_reg_operand" "<SFDF:Ff>,<SFDF:Ff>"))
+ (match_operand:SFDF 3 "gpc_reg_operand" "d,d"))
(set (match_operand:P 0 "gpc_reg_operand" "=b,b")
(plus:P (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_UPDATE
@@ -14142,11 +14139,11 @@ (define_expand "fma<mode>4"
"")
(define_insn "*fma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))]
"TARGET_HARD_FLOAT"
"@
fmadd<s> %0,%1,%2,%3
@@ -14166,11 +14163,11 @@ (define_expand "fms<mode>4"
"")
(define_insn "*fms<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
- (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
fmsub<s> %0,%1,%2,%3
@@ -14213,12 +14210,12 @@ (define_expand "nfma<mode>4"
"")
(define_insn "*nfma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
fnmadd<s> %0,%1,%2,%3
@@ -14239,13 +14236,13 @@ (define_expand "nfms<mode>4"
"")
(define_insn "*nfmssf4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
+ (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0")
(neg:SFDF
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
+ (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))))]
"TARGET_HARD_FLOAT"
"@
fnmsub<s> %0,%1,%2,%3
--
1.8.3.1
