Enable optimization for TImode only under 32-bit target, for 64-bit
target there could be extra ineteger <-> sse move regarding psABI,
not efficient.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}
Ok for trunk?
gcc/ChangeLog:
PR target/104610
* config/i386/i386-expand.cc (ix86_expand_branch): Use ptest
for TI/QImode when code is EQ or NE.
* config/i386/i386.md (SDWIM1248): New iterator.
(cbranch<mode>4): Split TImode into a separate expander.
(cbranchti4): New expander.
* config/i386/predicates.md (timode_comparison_operator): New
predicate.
* config/i386/sse.md (cbranch<mode>4): Extend to OImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr104610.c: New test.
---
gcc/config/i386/i386-expand.cc | 13 +++++++++++-
gcc/config/i386/i386.md | 27 ++++++++++++++++++++++--
gcc/config/i386/predicates.md | 6 ++++++
gcc/config/i386/sse.md | 10 +++++++--
gcc/testsuite/gcc.target/i386/pr104610.c | 23 ++++++++++++++++++++
5 files changed, 74 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr104610.c
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index bc806ffa283..a2012a158ae 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2264,13 +2264,24 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx
op1, rtx label)
{
machine_mode mode = GET_MODE (op0);
rtx tmp;
+ machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
+ /* Using ptest for TImode only for 32-bit target since it's splitted into
+ 4 comparisons. For 64-bit target there could be extra ineteger <-> sse
+ move regarding psABI, not efficient. */
+ if ((code == EQ || code == NE)
+ && ((mode == OImode && TARGET_AVX)
+ || (mode == TImode && !TARGET_64BIT && TARGET_SSE4_1)))
+ {
+ op0 = lowpart_subreg (p_mode, force_reg (mode, op0), mode);
+ op1 = lowpart_subreg (p_mode, force_reg (mode, op1), mode);
+ mode = p_mode;
+ }
/* Handle special case - vector comparsion with boolean result, transform
it using ptest instruction. */
if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
{
rtx flag = gen_rtx_REG (CCZmode, FLAGS_REG);
- machine_mode p_mode = GET_MODE_SIZE (mode) == 32 ? V4DImode : V2DImode;
gcc_assert (code == EQ || code == NE);
/* Generate XOR since we can't check that one operand is zero vector. */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b321cda1f22..f91325015c9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1069,6 +1069,10 @@ (define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
(HI "TARGET_HIMODE_MATH")
SI DI (TI "TARGET_64BIT")])
+(define_mode_iterator SDWIM1248 [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI DI])
+
;; Math-dependant single word integer modes.
(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
(HI "TARGET_HIMODE_MATH")
@@ -1322,8 +1326,8 @@ (define_mode_iterator PTR
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
- (match_operand:SDWIM 2 "<general_operand>")))
+ (compare:CC (match_operand:SDWIM1248 1 "nonimmediate_operand")
+ (match_operand:SDWIM1248 2 "<general_operand>")))
(set (pc) (if_then_else
(match_operator 0 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
@@ -1338,6 +1342,25 @@ (define_expand "cbranch<mode>4"
DONE;
})
+(define_expand "cbranchti4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:TI 1 "nonimmediate_operand")
+ (match_operand:TI 2 "x86_64_general_operand")))
+ (set (pc) (if_then_else
+ (match_operator 0 "timode_comparison_operator"
+ [(reg:CC FLAGS_REG) (const_int 0)])
+ (label_ref (match_operand 3))
+ (pc)))]
+ "TARGET_64BIT || TARGET_SSE4_1"
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (TImode, operands[1]);
+
+ ix86_expand_branch (GET_CODE (operands[0]),
+ operands[1], operands[2], operands[3]);
+ DONE;
+})
+
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index a8cc17a054d..fb3be3a262f 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1414,6 +1414,12 @@ (define_predicate "ix86_comparison_uns_operator"
(define_predicate "bt_comparison_operator"
(match_code "ne,eq"))
+(define_predicate "timode_comparison_operator"
+ (ior (and (match_test "TARGET_SSE4_1")
+ (match_operand 0 "bt_comparison_operator"))
+ (and (match_test "TARGET_64BIT")
+ (match_operand 0 "ordered_comparison_operator"))))
+
(define_predicate "shr_comparison_operator"
(match_code "gtu,leu"))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7b791def542..0d194cee769 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -26034,10 +26034,14 @@ (define_expand "maskstore<mode><avx512fmaskmodelower>"
(match_operand:<avx512fmaskmode> 2 "register_operand")))]
"TARGET_AVX512BW")
+(define_mode_iterator VI48_OI_AVX
+ [(V8SI "TARGET_AVX") (V4DI "TARGET_AVX") (OI "TARGET_AVX")
+ V4SI V2DI])
+
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:VI48_AVX 1 "register_operand")
- (match_operand:VI48_AVX 2 "nonimmediate_operand")))
+ (compare:CC (match_operand:VI48_OI_AVX 1 "register_operand")
+ (match_operand:VI48_OI_AVX 2 "nonimmediate_operand")))
(set (pc) (if_then_else
(match_operator 0 "bt_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
@@ -26045,6 +26049,8 @@ (define_expand "cbranch<mode>4"
(pc)))]
"TARGET_SSE4_1"
{
+ if (!vector_operand (operands[2], <MODE>mode))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
diff --git a/gcc/testsuite/gcc.target/i386/pr104610.c
b/gcc/testsuite/gcc.target/i386/pr104610.c
new file mode 100644
index 00000000000..68f548594fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104610.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmove-max=256 -mstore-max=256" } */
+/* { dg-final { scan-assembler-times {(?n)ptest.*xmm} 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times {(?n)vptest.*ymm} 1 } } */
+/* { dg-final { scan-assembler-times {sete} 2 } } */
+/* { dg-final { scan-assembler-not {(?n)je.*L[0-9]} } } */
+/* { dg-final { scan-assembler-not {(?n)jne.*L[0-9]} } } */
+
+
+#include<stdbool.h>
+__attribute__((target("sse4.1")))
+bool f128(char *a)
+{
+ char t[] = "012345678901234";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
+
+__attribute__((target("avx")))
+bool f256(char *a)
+{
+ char t[] = "0123456789012345678901234567890";
+ return __builtin_memcmp(a, &t[0], sizeof(t)) == 0;
+}
--
2.18.1
