Optimize _mm_storeu_si16 to use MOVD from a SSE to an integer register
instead of PEXTRW from a low word of the SSE register to an integer reg.
Avoid the transformation when optimizing for size for targets without
TARGET_INTER_UNIT_MOVES_FROM_VEC capability, where the transformation
results in two moves via a memory location.
2022-05-03 Uroš Bizjak <ubiz...@gmail.com>
gcc/ChangeLog:
PR target/105079
* config/i386/sse.md (*vec_extract<mode>_0_mem): New pre-reload
define_insn_and_split pattern.
gcc/testsuite/ChangeLog:
PR target/105079
* gcc.target/i386/pr105079.c: New test.
* gcc.target/i386/pr95483-1.c (dg-options): Use -msse4.1.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Pushed to master.
Uros.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5e93aa23b47..7b791def542 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -19021,6 +19021,26 @@ (define_insn "sse2_loadld"
(define_mode_iterator PEXTR_MODE12
[(V16QI "TARGET_SSE4_1") V8HI])
+(define_insn_and_split "*vec_extract<mode>_0_mem"
+ [(set (match_operand:<ssescalarmode> 0 "memory_operand")
+ (vec_select:<ssescalarmode>
+ (match_operand:PEXTR_MODE12 1 "register_operand")
+ (parallel [(const_int 0)])))]
+ "TARGET_SSE2
+ && !TARGET_SSE4_1
+ && (TARGET_INTER_UNIT_MOVES_FROM_VEC
+ || optimize_function_for_speed_p (cfun))
+ && ix86_pre_reload_split ()"
+ "#"
+ "&& 1"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 0) (match_dup 4))]
+{
+ operands[2] = gen_reg_rtx (SImode);
+ operands[3] = gen_lowpart (SImode, force_reg (<MODE>mode, operands[1]));
+ operands[4] = gen_lowpart (<ssescalarmode>mode, operands[2]);
+})
+
(define_insn "*vec_extract<mode>"
[(set (match_operand:<ssescalarmode> 0 "register_sse4nonimm_operand" "=r,m")
(vec_select:<ssescalarmode>
diff --git a/gcc/testsuite/gcc.target/i386/pr105079.c
b/gcc/testsuite/gcc.target/i386/pr105079.c
new file mode 100644
index 00000000000..4ecf864afde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105079.c
@@ -0,0 +1,11 @@
+/* PR target/105079 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-sse4.1" } */
+/* { dg-final { scan-assembler-not "pextrw" } } */
+
+#include <xmmintrin.h>
+
+void store16 (void *p, __m128i v)
+{
+ _mm_storeu_si16 (p, v);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr95483-1.c
b/gcc/testsuite/gcc.target/i386/pr95483-1.c
index 0f3e0bf9280..26b2e8275eb 100644
--- a/gcc/testsuite/gcc.target/i386/pr95483-1.c
+++ b/gcc/testsuite/gcc.target/i386/pr95483-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -msse2" } */
+/* { dg-options "-O2 -msse4.1" } */
/* { dg-final { scan-assembler-times "pxor\[
\\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "pinsrw\[
\\t\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "pextrw\[
\\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*(?:\n|\[ \\t\]+#)" 1 } } */
