On Wed, Mar 16, 2022 at 6:50 PM Jakub Jelinek <ja...@redhat.com> wrote: > > Hi! > > I'd like to ping this patch: > https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590960.html > > Thanks. > > On Mon, Feb 28, 2022 at 07:06:30AM +0100, Jakub Jelinek wrote: > > As mentioned in the PR, the latest Intel SDM has added: > > "Processors that enumerate support for Intel® AVX (by setting the feature > > flag CPUID.01H:ECX.AVX[bit 28]) > > guarantee that the 16-byte memory operations performed by the following > > instructions will always be > > carried out atomically: > > • MOVAPD, MOVAPS, and MOVDQA. > > • VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. > > • VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded with EVEX.128 and > > k0 (masking disabled). > > (Note that these instructions require the linear addresses of their memory > > operands to be 16-byte > > aligned.)" > > > > The following patch deals with it just on the libatomic library side so far, > > currently (since ~ 2017) we emit all the __atomic_* 16-byte builtins as > > library calls since and this is something that we can hopefully backport. > > > > The patch simply introduces yet another ifunc variant that takes priority > > over the pure CMPXCHG16B one, one that checks AVX and CMPXCHG16B bits and > > on non-Intel clears the AVX bit during detection for now (if AMD comes > > with the same guarantee, we could revert the config/x86/init.c hunk), > > which implements 16-byte atomic load as vmovdqa and 16-byte atomic store > > as vmovdqa followed by mfence. > > > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk so far? > > > > 2022-02-28 Jakub Jelinek <ja...@redhat.com> > > > > PR target/104688 > > * Makefile.am (IFUNC_OPTIONS): Change on x86_64 to -mcx16 -mcx16. > > (libatomic_la_LIBADD): Add $(addsuffix _16_2_.lo,$(SIZEOBJS)) for > > x86_64. > > * Makefile.in: Regenerated. > > * config/x86/host-config.h (IFUNC_COND_1): For x86_64 define to > > both AVX and CMPXCHG16B bits. > > (IFUNC_COND_2): Define. > > (IFUNC_NCOND): For x86_64 define to 2 * (N == 16). > > (MAYBE_HAVE_ATOMIC_CAS_16, MAYBE_HAVE_ATOMIC_EXCHANGE_16, > > MAYBE_HAVE_ATOMIC_LDST_16): Define to IFUNC_COND_2 rather than > > IFUNC_COND_1. > > (HAVE_ATOMIC_CAS_16): Redefine to 1 whenever IFUNC_ALT != 0. > > (HAVE_ATOMIC_LDST_16): Redefine to 1 whenever IFUNC_ALT == 1. > > (atomic_compare_exchange_n): Define whenever IFUNC_ALT != 0 > > on x86_64 for N == 16. > > (__atomic_load_n, __atomic_store_n): Redefine whenever IFUNC_ALT == 1 > > on x86_64 for N == 16. > > (atomic_load_n, atomic_store_n): New functions. > > * config/x86/init.c (__libat_feat1_init): On x86_64 clear bit_AVX > > if CPU vendor is not Intel.
LGTM. Thanks, Uros.
