This simple i386 patch unblocks a more significant change. The testcase
gcc.target/i386/sse2-pr94680.c isn't quite testing what's intended, and
alas the fix for PR target/94680 doesn't (yet) handle V2DF mode.
For the first test from sse2-pr94680.c, below
v2df foo_v2df (v2df x) {
return __builtin_shuffle (x, (v2df) { 0, 0 }, (v2di) { 0, 2 });
}
GCC on x86_64-pc-linux-gnu with -O2 currently generates:
movhpd .LC0(%rip), %xmm0
ret
.LC0:
.long 0
.long 0
which passes the test as it contains a mov insn and no xor.
Alas reading a zero from the constant pool isn't quite the
desired implementation. With this patch we now generate:
movq %xmm0, %xmm0
ret
The same code as we generate for V2DI, and add a stricter
test case. My first attempt tried using VI8F_128 to generalize
the existing sse2_movq128 define_insn to both V2DI and V2DF.
Alas, CODE_FOR_sse2_movq128 is exposed as a builtin in
i386-builtin.def, requiring some internal name changes, that
ultimately the testsuite was unhappy with. The simpler solution
(that works) is to clone/specialize a new V2DF *sse2_movq128_2.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check with no new failures. Ok for mainline?
2022-03-15 Roger Sayle <ro...@nextmovesoftware.com>
gcc/ChangeLog
PR target/94680
* config/i386/sse.md (*sse2_movq128_2): A version of sse2_movq128
for V2DF mode.
gcc/testsuite/ChangeLog
PR target/94680
* gcc.target/i386/sse2-pr94680-2.c: New stricter V2DF test case.
Thanks in advance,
Roger
--
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e9292e6..d017fb8 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1599,6 +1599,19 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
+(define_insn "*sse2_movq128_2"
+ [(set (match_operand:V2DF 0 "register_operand" "=v")
+ (vec_concat:V2DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "nonimmediate_operand" "vm")
+ (parallel [(const_int 0)]))
+ (match_operand:DF 2 "const0_operand")))]
+ "TARGET_SSE2"
+ "%vmovq\t{%1, %0|%0, %q1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
+
;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
;; from memory, we'd prefer to load the memory directly into the %xmm
diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c
b/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c
new file mode 100644
index 0000000..abd260a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+typedef double v2df __attribute__ ((vector_size (16)));
+typedef long long v2di __attribute__((vector_size(16)));
+
+v2df foo_v2df (v2df x)
+{
+ return __builtin_shuffle (x, (v2df) { 0, 0 }, (v2di) { 0, 2 });
+}
+
+/* { dg-final { scan-assembler "movq" } } */
+/* { dg-final { scan-assembler-not "pxor" } } */
+
