On Thu, Jan 6, 2022 at 7:00 PM Roger Sayle <ro...@nextmovesoftware.com> wrote:
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> This patch improves the code generated when moving a 128-bit value
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> in TImode, represented by two 64-bit registers, to V1TImode, which
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> is a single SSE register.
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>
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> Currently, the simple move:
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> typedef unsigned __int128 uv1ti __attribute__ ((__vector_size__ (16)));
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> uv1ti foo(__int128 x) { return (uv1ti)x; }
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> is always transferred via memory, as:
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> foo: movq %rdi, -24(%rsp)
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> movq %rsi, -16(%rsp)
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> movdqa -24(%rsp), %xmm0
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> ret
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>
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> with this patch, we now generate (with -msse2):
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> foo: movq %rdi, %xmm1
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> movq %rsi, %xmm2
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> punpcklqdq %xmm2, %xmm1
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> movdqa %xmm1, %xmm0
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> ret
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>
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> and with -mavx2:
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> foo: vmovq %rdi, %xmm1
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> vpinsrq $1, %rsi, %xmm1, %xmm0
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> ret
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> Even more dramatic is the improvement of zero extended transfers.
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> uv1ti bar(unsigned char c) { return (uv1ti)(__int128)c; }
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> Previously generated:
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> bar: movq $0, -16(%rsp)
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> movzbl %dil, %eax
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> movq %rax, -24(%rsp)
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> vmovdqa -24(%rsp), %xmm0
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> ret
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> Now generates:
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> bar: movzbl %dil, %edi
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> movq %rdi, %xmm0
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> ret
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> My first attempt at this functionality attempted to use a
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> simple define_split:
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> +;; Move TImode to V1TImode via V2DImode instead of memory.
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> +(define_split
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> + [(set (match_operand:V1TI 0 "register_operand")
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> + (subreg:V1TI (match_operand:TI 1 "register_operand") 0))]
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> + "TARGET_64BIT && TARGET_SSE2 && can_create_pseudo_p ()"
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> + [(set (match_dup 2) (vec_concat:V2DI (match_dup 3) (match_dup 4)))
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> + (set (match_dup 0) (subreg:V1TI (match_dup 2) 0))]
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> +{
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> + operands[2] = gen_reg_rtx (V2DImode);
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> + operands[3] = gen_lowpart (DImode, operands[1]);
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> + operands[4] = gen_highpart (DImode, operands[1]);
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> +})
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> +
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> Unfortunately, this triggers very late during the compilation
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> preventing some of the simplification's we'd like (in combine).
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> For example the foo case above becomes:
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>
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> foo: movq %rsi, -16(%rsp)
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> movq %rdi, %xmm0
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> movhps -16(%rsp), %xmm0
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>
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> transferring half directly, and the other half via memory.
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> And for the bar case above, GCC fails to appreciate that
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> movq/vmovq clears the high bits, resulting in:
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>
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> bar: movzbl %dil, %eax
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> xorl %edx, %edx
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> vmovq %rax, %xmm1
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> vpinsrq $1, %rdx, %xmm1, %xmm0
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> ret
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> Hence the solution (i.e. this patch) is to add a special case
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> to ix86_expand_vector_move for TImode to V1TImode transfers.
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> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
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> and make -k check with no new failures. Ok for mainline?
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> 2022-01-06 Roger Sayle <ro...@nextmovesoftware.com>
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> gcc/ChangeLog
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> * config/i386/i386-expand.c (ix86_expand_vector_move): Add
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> special case for TImode to V1TImode moves, going via V2DImode.
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>
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> gcc/testsuite/ChangeLog
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> * gcc.target/i386/sse2-v1ti-mov-1.c: New test case.
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> * gcc.target/i386/sse2-v1ti-zext.c: New test case.
OK.
Thanks,
Uros.
