When applying peephole optimization to transform
mov imm, %reg0
mov %reg1, %AX_REG
imul %reg0
to
mov imm, %AX_REG
imul %reg1
disable peephole optimization if reg1 == AX_REG as in
(set (reg:SI 1 dx [92])
(const_int 714200473 [0x2a91d599]))
(set (reg:SI 0 ax [105])
(reg:SI 0 ax [orig:89 k ] [89]))
(parallel [
(set (reg:SI 1 dx [91])
(smul_highpart:SI (reg:SI 0 ax [105]) (reg:SI 1 dx [92])))
(clobber (reg:SI 0 ax [105]))
(clobber (reg:CC 17 flags))
])
PR bootstrap/103785
* config/i386/i386.md: Swap operand order in comments and check
AX input in any_mul_highpart peepholes.
---
gcc/config/i386/i386.md | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 58b10643fcb..72e6486a92f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -8552,7 +8552,7 @@
(set_attr "mode" "SI")])
;; Highpart multiplication peephole2s to tweak register allocation.
-;; mov %rdx,imm; mov %rax,%rdi; imulq %rdx -> mov %rax,imm; imulq %rdi
+;; mov imm,%rdx; mov %rdi,%rax; imulq %rdx -> mov imm,%rax; imulq %rdi
(define_peephole2
[(set (match_operand:SWI48 0 "general_reg_operand")
(match_operand:SWI48 1 "immediate_operand"))
@@ -8562,7 +8562,8 @@
(any_mul_highpart:SWI48 (match_dup 2) (match_dup 0)))
(clobber (match_dup 2))
(clobber (reg:CC FLAGS_REG))])]
- "REGNO (operands[0]) != REGNO (operands[2])
+ "REGNO (operands[3]) != AX_REG
+ && REGNO (operands[0]) != REGNO (operands[2])
&& REGNO (operands[0]) != REGNO (operands[3])
&& (REGNO (operands[0]) == REGNO (operands[4])
|| peep2_reg_dead_p (3, operands[0]))"
@@ -8582,7 +8583,9 @@
(any_mul_highpart:SI (match_dup 2) (match_dup 0))))
(clobber (match_dup 2))
(clobber (reg:CC FLAGS_REG))])]
- "REGNO (operands[0]) != REGNO (operands[2])
+ "REGNO (operands[3]) != AX_REG
+ && REGNO (operands[0]) != REGNO (operands[2])
+ && REGNO (operands[2]) != REGNO (operands[3])
&& REGNO (operands[0]) != REGNO (operands[3])
&& (REGNO (operands[0]) == REGNO (operands[4])
|| peep2_reg_dead_p (3, operands[0]))"
--
2.33.1
