On Mon, Dec 13, 2021 at 1:09 PM Roger Sayle <ro...@nextmovesoftware.com> wrote:
>
>
> I'll post my proposed fix for PR target/103611 shortly, but this patch
> fixes another missed optimization opportunity revealed by that PR.
> Occasionally, reload materializes integer constants during register
> allocation sometimes resulting in unnecessary instructions such as:
>
> (insn 23 31 24 2 (parallel [
> (set (reg:SI 0 ax [99])
> (ior:SI (reg:SI 0 ax [99])
> (const_int 0 [0])))
> (clobber (reg:CC 17 flags))
> ]) "pr103611.c":18:73 550 {*iorsi_1}
> (nil))
>
> These then get "optimized" during the split2 pass, which realizes that
> no bits outside of 0xff00 are set, so this operation can be implemented
> by operating on just the highpart of a QIreg_operand, i.e. %ah, %bh, %ch
> etc., which leads to the useless "orb $0, %ah" seen in the reported PR.
>
> This fix catches the case of const0_rtx in relevant splitter, either
> eliminating the instruction or turning it into a simple move.
>
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> and make -k check, both with and without "--target_board='unix{-m32}'"
> with no new failures. OK for mainline?
>
>
> 2021-12-13 Roger Sayle <ro...@nextmovesoftware.com>
>
> gcc/ChangeLog
> * config/i386/i386.md (define_split any_or:SWI248 -> orb %?h):
> Optimize the case where the integer constant operand is zero.
>
> gcc/testsuite/ChangeLog
> * gcc.target/i386/pr103611-1.c: New test case.
OK with a small testsuite adjustment.
Thanks,
Uros.
+/* { dg-do compile } */
+/* { dg-options "-m32 -O2 -msse4" } */
Please add target selector to dg-do compile directive instead of an
explicit -m32 to dg-options, e.g.:
/* { dg-do compile { target ia32 } } */
