On Wed, Nov 10, 2021 at 1:44 PM Richard Sandiford via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> This patch adds conditional forms of FMAX and FMIN, following
> the pattern for existing conditional binary functions.
>
> Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
OK.
Thanks,
Richard.
> Richard
>
>
> gcc/
> * doc/md.texi (cond_fmin@var{mode}, cond_fmax@var{mode}): Document.
> * optabs.def (cond_fmin_optab, cond_fmax_optab): New optabs.
> * internal-fn.def (COND_FMIN, COND_FMAX): New functions.
> * internal-fn.c (first_commutative_argument): Handle them.
> (FOR_EACH_COND_FN_PAIR): Likewise.
> * match.pd (UNCOND_BINARY, COND_BINARY): Likewise.
> * config/aarch64/aarch64-sve.md (cond_<fmaxmin><mode>): New
> pattern.
>
> gcc/testsuite/
> * gcc.target/aarch64/sve/cond_fmaxnm_5.c: New test.
> * gcc.target/aarch64/sve/cond_fmaxnm_5_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_6.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_6_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_7.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_7_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_8.c: Likewise.
> * gcc.target/aarch64/sve/cond_fmaxnm_8_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_5.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_5_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_6.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_6_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_7.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_7_run.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_8.c: Likewise.
> * gcc.target/aarch64/sve/cond_fminnm_8_run.c: Likewise.
> ---
> gcc/config/aarch64/aarch64-sve.md | 19 +++++++++++-
> gcc/doc/md.texi | 4 +++
> gcc/internal-fn.c | 4 +++
> gcc/internal-fn.def | 2 ++
> gcc/match.pd | 2 ++
> gcc/optabs.def | 2 ++
> .../gcc.target/aarch64/sve/cond_fmaxnm_5.c | 28 ++++++++++++++++++
> .../aarch64/sve/cond_fmaxnm_5_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fmaxnm_6.c | 22 ++++++++++++++
> .../aarch64/sve/cond_fmaxnm_6_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fmaxnm_7.c | 27 +++++++++++++++++
> .../aarch64/sve/cond_fmaxnm_7_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fmaxnm_8.c | 26 +++++++++++++++++
> .../aarch64/sve/cond_fmaxnm_8_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fminnm_5.c | 29 +++++++++++++++++++
> .../aarch64/sve/cond_fminnm_5_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fminnm_6.c | 23 +++++++++++++++
> .../aarch64/sve/cond_fminnm_6_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fminnm_7.c | 28 ++++++++++++++++++
> .../aarch64/sve/cond_fminnm_7_run.c | 4 +++
> .../gcc.target/aarch64/sve/cond_fminnm_8.c | 27 +++++++++++++++++
> .../aarch64/sve/cond_fminnm_8_run.c | 4 +++
> 22 files changed, 274 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
>
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index 5de479e141a..0f5bf5ea8cb 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -6287,7 +6287,7 @@ (define_expand "xorsign<mode>3"
> ;; -------------------------------------------------------------------------
>
> ;; Unpredicated fmax/fmin (the libm functions). The optabs for the
> -;; smin/smax rtx codes are handled in the generic section above.
> +;; smax/smin rtx codes are handled in the generic section above.
> (define_expand "<fmaxmin><mode>3"
> [(set (match_operand:SVE_FULL_F 0 "register_operand")
> (unspec:SVE_FULL_F
> @@ -6302,6 +6302,23 @@ (define_expand "<fmaxmin><mode>3"
> }
> )
>
> +;; Predicated fmax/fmin (the libm functions). The optabs for the
> +;; smax/smin rtx codes are handled in the generic section above.
> +(define_expand "cond_<fmaxmin><mode>"
> + [(set (match_operand:SVE_FULL_F 0 "register_operand")
> + (unspec:SVE_FULL_F
> + [(match_operand:<VPRED> 1 "register_operand")
> + (unspec:SVE_FULL_F
> + [(match_dup 1)
> + (const_int SVE_RELAXED_GP)
> + (match_operand:SVE_FULL_F 2 "register_operand")
> + (match_operand:SVE_FULL_F 3 "aarch64_sve_float_maxmin_operand")]
> + SVE_COND_FP_MAXMIN_PUBLIC)
> + (match_operand:SVE_FULL_F 4 "aarch64_simd_reg_or_zero")]
> + UNSPEC_SEL))]
> + "TARGET_SVE"
> +)
> +
> ;; Predicated floating-point maximum/minimum.
> (define_insn "@aarch64_pred_<optab><mode>"
> [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, w, ?&w, ?&w")
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 41f1850bf6e..589f841ea74 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -6930,6 +6930,8 @@ operand 0, otherwise (operand 2 + operand 3) is moved.
> @cindex @code{cond_smax@var{mode}} instruction pattern
> @cindex @code{cond_umin@var{mode}} instruction pattern
> @cindex @code{cond_umax@var{mode}} instruction pattern
> +@cindex @code{cond_fmin@var{mode}} instruction pattern
> +@cindex @code{cond_fmax@var{mode}} instruction pattern
> @cindex @code{cond_ashl@var{mode}} instruction pattern
> @cindex @code{cond_ashr@var{mode}} instruction pattern
> @cindex @code{cond_lshr@var{mode}} instruction pattern
> @@ -6947,6 +6949,8 @@ operand 0, otherwise (operand 2 + operand 3) is moved.
> @itemx @samp{cond_smax@var{mode}}
> @itemx @samp{cond_umin@var{mode}}
> @itemx @samp{cond_umax@var{mode}}
> +@itemx @samp{cond_fmin@var{mode}}
> +@itemx @samp{cond_fmax@var{mode}}
> @itemx @samp{cond_ashl@var{mode}}
> @itemx @samp{cond_ashr@var{mode}}
> @itemx @samp{cond_lshr@var{mode}}
> diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
> index 0cba95411a6..da7d8355214 100644
> --- a/gcc/internal-fn.c
> +++ b/gcc/internal-fn.c
> @@ -3840,6 +3840,8 @@ first_commutative_argument (internal_fn fn)
> case IFN_COND_MUL:
> case IFN_COND_MIN:
> case IFN_COND_MAX:
> + case IFN_COND_FMIN:
> + case IFN_COND_FMAX:
> case IFN_COND_AND:
> case IFN_COND_IOR:
> case IFN_COND_XOR:
> @@ -3959,6 +3961,8 @@ conditional_internal_fn_code (internal_fn ifn)
> /* Invoke T(IFN) for each internal function IFN that also has an
> IFN_COND_* form. */
> #define FOR_EACH_COND_FN_PAIR(T) \
> + T (FMAX) \
> + T (FMIN) \
> T (FMA) \
> T (FMS) \
> T (FNMA) \
> diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
> index bb13c6cce1b..bb4d8ab8096 100644
> --- a/gcc/internal-fn.def
> +++ b/gcc/internal-fn.def
> @@ -188,6 +188,8 @@ DEF_INTERNAL_SIGNED_OPTAB_FN (COND_MIN, ECF_CONST, first,
> cond_smin, cond_umin, cond_binary)
> DEF_INTERNAL_SIGNED_OPTAB_FN (COND_MAX, ECF_CONST, first,
> cond_smax, cond_umax, cond_binary)
> +DEF_INTERNAL_OPTAB_FN (COND_FMIN, ECF_CONST, cond_fmin, cond_binary)
> +DEF_INTERNAL_OPTAB_FN (COND_FMAX, ECF_CONST, cond_fmax, cond_binary)
> DEF_INTERNAL_OPTAB_FN (COND_AND, ECF_CONST | ECF_NOTHROW,
> cond_and, cond_binary)
> DEF_INTERNAL_OPTAB_FN (COND_IOR, ECF_CONST | ECF_NOTHROW,
> diff --git a/gcc/match.pd b/gcc/match.pd
> index a319aefa808..f7884944571 100644
> --- a/gcc/match.pd
> +++ b/gcc/match.pd
> @@ -90,12 +90,14 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> plus minus
> mult trunc_div trunc_mod rdiv
> min max
> + IFN_FMIN IFN_FMAX
> bit_and bit_ior bit_xor
> lshift rshift)
> (define_operator_list COND_BINARY
> IFN_COND_ADD IFN_COND_SUB
> IFN_COND_MUL IFN_COND_DIV IFN_COND_MOD IFN_COND_RDIV
> IFN_COND_MIN IFN_COND_MAX
> + IFN_COND_FMIN IFN_COND_FMAX
> IFN_COND_AND IFN_COND_IOR IFN_COND_XOR
> IFN_COND_SHL IFN_COND_SHR)
>
> diff --git a/gcc/optabs.def b/gcc/optabs.def
> index b889ad2e5a0..e25f4c9a346 100644
> --- a/gcc/optabs.def
> +++ b/gcc/optabs.def
> @@ -241,6 +241,8 @@ OPTAB_D (cond_smin_optab, "cond_smin$a")
> OPTAB_D (cond_smax_optab, "cond_smax$a")
> OPTAB_D (cond_umin_optab, "cond_umin$a")
> OPTAB_D (cond_umax_optab, "cond_umax$a")
> +OPTAB_D (cond_fmin_optab, "cond_fmin$a")
> +OPTAB_D (cond_fmax_optab, "cond_fmax$a")
> OPTAB_D (cond_fma_optab, "cond_fma$a")
> OPTAB_D (cond_fms_optab, "cond_fms$a")
> OPTAB_D (cond_fnma_optab, "cond_fnma$a")
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
> new file mode 100644
> index 00000000000..4bae7e02de4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_1.c"
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
> new file mode 100644
> index 00000000000..1aa2eb4f537
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_1_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
> new file mode 100644
> index 00000000000..912db00466e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6.c
> @@ -0,0 +1,22 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_2.c"
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
> new file mode 100644
> index 00000000000..19f6eddb839
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_6_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_2_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
> new file mode 100644
> index 00000000000..30f07f62ddb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_3.c"
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
> new file mode 100644
> index 00000000000..3e647ed914f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_3_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
> new file mode 100644
> index 00000000000..a590d382b6a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_4.c"
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z,
> z[0-9]+\.s\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z,
> z[0-9]+\.d\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
> new file mode 100644
> index 00000000000..d421e54f996
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_8_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fmaxnm_4_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
> new file mode 100644
> index 00000000000..290c4beac24
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#define FN(X) __builtin_fmin##X
> +#include "cond_fmaxnm_1.c"
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
> new file mode 100644
> index 00000000000..76baf6a96f5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fminnm_1_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
> new file mode 100644
> index 00000000000..cc9db999cbd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6.c
> @@ -0,0 +1,23 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#define FN(X) __builtin_fmin##X
> +#include "cond_fmaxnm_2.c"
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
> new file mode 100644
> index 00000000000..dbafea1ac6b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_6_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fminnm_2_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
> new file mode 100644
> index 00000000000..347a1a3540b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#define FN(X) __builtin_fmin##X
> +#include "cond_fmaxnm_3.c"
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
> z[0-9]+\.h\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
> new file mode 100644
> index 00000000000..6617095fea0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fminnm_3_run.c"
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
> new file mode 100644
> index 00000000000..20d6cb505fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#define FN(X) __builtin_fmin##X
> +#include "cond_fmaxnm_4.c"
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #0\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #0\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, #1\.0\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, #1\.0\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
> z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
> z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
> +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
> z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
> +
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z,
> z[0-9]+\.s\n} 3 } } */
> +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.d, p[0-7]/z,
> z[0-9]+\.d\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-not {\tmov\tz} } } */
> +/* { dg-final { scan-assembler-not {\tsel\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
> b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
> new file mode 100644
> index 00000000000..4fb649727d0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_8_run.c
> @@ -0,0 +1,4 @@
> +/* { dg-do run { target aarch64_sve_hw } } */
> +/* { dg-options "-O2 -ftree-vectorize" } */
> +
> +#include "cond_fminnm_4_run.c"
> --
> 2.25.1
>
