Richard Sandiford via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>> This patch covers a few builtins where we do not use the <mode>
>> iterator and thus we cannot use <MVE_vpred>.
>>
>> However this introduces a problem for the v2di instructions, because
>> there is not predicate for this case. For instance, changing
>> STRSBS_P_QUALIFIERS breaks mve_vstrdq_scatter_base_p_<supf>v2di.
>> Similarly, this patch introduces problems with:
>> mve_vldrdq_gather_base_z_<supf>v2di
>> mve_vldrdq_gather_base_wb_z_<supf>v2di
>> mve_vldrdq_gather_base_nowb_z_<supf>v2di
>> mve_vstrdq_scatter_base_wb_p_<supf>v2di
>
> I think we should treat HImode as the predicate mode for V2DI,
> alongside the others, even though it isn't a vector boolean mode.
> Like you say, it'll end up being too much of a special case otherwise.
Actually: couldn't we have a V8BI too? Sorry, I was getting confused
with something else and thought that that wouldn't be possible for
some reason.
V8BI might not be used as much as the other boolean modes, but it still
seems like conceptually the right thing to do.
Thanks,
Richard
>
> Thanks,
> Richard
>
>> 2021-09-02 Christophe Lyon <christophe.l...@foss.st.com>
>>
>> gcc/
>> PR target/100757
>> PR target/101325
>> * config/arm/arm-builtins.c (STRSBS_P_QUALIFIERS): Use predicate
>> qualifier.
>> (STRSBU_P_QUALIFIERS): Likewise.
>> (LDRGBS_Z_QUALIFIERS): Likewise.
>> (LDRGBU_Z_QUALIFIERS): Likewise.
>> (LDRGBWBXU_Z_QUALIFIERS): Likewise.
>> (LDRGBWBS_Z_QUALIFIERS): Likewise.
>> (LDRGBWBU_Z_QUALIFIERS): Likewise.
>> (STRSBWBS_P_QUALIFIERS): Likewise.
>> (STRSBWBU_P_QUALIFIERS): Likewise.
>> * config/arm/mve.md: Use VxBI instead of HI.
>>
>> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
>> index 06ff9d2278a..e58580bb828 100644
>> --- a/gcc/config/arm/arm-builtins.c
>> +++ b/gcc/config/arm/arm-builtins.c
>> @@ -738,13 +738,13 @@ arm_strss_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> static enum arm_type_qualifiers
>> arm_strsbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_void, qualifier_unsigned, qualifier_immediate,
>> - qualifier_none, qualifier_unsigned};
>> + qualifier_none, qualifier_predicate};
>> #define STRSBS_P_QUALIFIERS (arm_strsbs_p_qualifiers)
>>
>> static enum arm_type_qualifiers
>> arm_strsbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_void, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned, qualifier_unsigned};
>> + qualifier_unsigned, qualifier_predicate};
>> #define STRSBU_P_QUALIFIERS (arm_strsbu_p_qualifiers)
>>
>> static enum arm_type_qualifiers
>> @@ -780,13 +780,13 @@ arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> static enum arm_type_qualifiers
>> arm_ldrgbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_none, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned};
>> + qualifier_predicate};
>> #define LDRGBS_Z_QUALIFIERS (arm_ldrgbs_z_qualifiers)
>>
>> static enum arm_type_qualifiers
>> arm_ldrgbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned};
>> + qualifier_predicate};
>> #define LDRGBU_Z_QUALIFIERS (arm_ldrgbu_z_qualifiers)
>>
>> static enum arm_type_qualifiers
>> @@ -826,7 +826,7 @@ arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> static enum arm_type_qualifiers
>> arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned};
>> + qualifier_predicate};
>> #define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers)
>>
>> static enum arm_type_qualifiers
>> @@ -842,13 +842,13 @@ arm_ldrgbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> static enum arm_type_qualifiers
>> arm_ldrgbwbs_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_none, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned};
>> + qualifier_predicate};
>> #define LDRGBWBS_Z_QUALIFIERS (arm_ldrgbwbs_z_qualifiers)
>>
>> static enum arm_type_qualifiers
>> arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
>> - qualifier_unsigned};
>> + qualifier_predicate};
>> #define LDRGBWBU_Z_QUALIFIERS (arm_ldrgbwbu_z_qualifiers)
>>
>> static enum arm_type_qualifiers
>> @@ -864,13 +864,13 @@ arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> static enum arm_type_qualifiers
>> arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_unsigned, qualifier_unsigned, qualifier_const,
>> - qualifier_none, qualifier_unsigned};
>> + qualifier_none, qualifier_predicate};
>> #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers)
>>
>> static enum arm_type_qualifiers
>> arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
>> = { qualifier_unsigned, qualifier_unsigned, qualifier_const,
>> - qualifier_unsigned, qualifier_unsigned};
>> + qualifier_unsigned, qualifier_predicate};
>> #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers)
>>
>> static enum arm_type_qualifiers
>> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
>> index 2f36d47c800..241195909da 100644
>> --- a/gcc/config/arm/mve.md
>> +++ b/gcc/config/arm/mve.md
>> @@ -7294,7 +7294,7 @@ (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
>> [(match_operand:V4SI 0 "s_register_operand" "w")
>> (match_operand:SI 1 "immediate_operand" "i")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWSBQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -7383,7 +7383,7 @@ (define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
>> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
>> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:SI 2 "immediate_operand" "i")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWGBQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -7621,7 +7621,7 @@ (define_insn "mve_vldrwq_<supf>v4si"
>> (define_insn "mve_vldrwq_z_fv4sf"
>> [(set (match_operand:V4SF 0 "s_register_operand" "=w")
>> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Ux")
>> - (match_operand:HI 2 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
>> VLDRWQ_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -7641,7 +7641,7 @@ (define_insn "mve_vldrwq_z_fv4sf"
>> (define_insn "mve_vldrwq_z_<supf>v4si"
>> [(set (match_operand:V4SI 0 "s_register_operand" "=w")
>> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Ux")
>> - (match_operand:HI 2 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
>> VLDRWQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -7825,7 +7825,7 @@ (define_insn "mve_vldrhq_gather_offset_z_fv8hf"
>> [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
>> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
>> (match_operand:V8HI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
>> VLDRHQGO_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -7867,7 +7867,7 @@ (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf"
>> [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
>> (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
>> (match_operand:V8HI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
>> VLDRHQGSO_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -7909,7 +7909,7 @@ (define_insn "mve_vldrwq_gather_base_z_fv4sf"
>> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
>> (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:SI 2 "immediate_operand" "i")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWQGB_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -7970,7 +7970,7 @@ (define_insn "mve_vldrwq_gather_offset_z_fv4sf"
>> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
>> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWQGO_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -7992,7 +7992,7 @@ (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si"
>> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
>> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWGOQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -8054,7 +8054,7 @@ (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf"
>> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
>> (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWQGSO_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -8076,7 +8076,7 @@ (define_insn
>> "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
>> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
>> (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VLDRWGSOQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -8116,7 +8116,7 @@ (define_insn "mve_vstrhq_fv8hf"
>> (define_insn "mve_vstrhq_p_fv8hf"
>> [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
>> (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")
>> - (match_operand:HI 2 "vpr_register_operand" "Up")]
>> + (match_operand:V8BI 2 "vpr_register_operand" "Up")]
>> VSTRHQ_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -8335,7 +8335,7 @@ (define_insn "mve_vstrwq_p_fv4sf"
>> (define_insn "mve_vstrwq_p_<supf>v4si"
>> [(set (match_operand:V4SI 0 "memory_operand" "=Ux")
>> (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
>> - (match_operand:HI 2 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 2 "vpr_register_operand" "Up")]
>> VSTRWQ))
>> ]
>> "TARGET_HAVE_MVE"
>> @@ -8588,7 +8588,7 @@ (define_expand "mve_vstrhq_scatter_offset_p_fv8hf"
>> [(match_operand:V8HI 0 "mve_scatter_memory")
>> (match_operand:V8HI 1 "s_register_operand")
>> (match_operand:V8HF 2 "s_register_operand")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V8BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -8606,7 +8606,7 @@ (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V8HI 1 "s_register_operand" "w")
>> (match_operand:V8HF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
>> VSTRHQSO_F))]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> "vpst\;vstrht.16\t%q2, [%0, %q1]"
>> @@ -8647,7 +8647,7 @@ (define_expand
>> "mve_vstrhq_scatter_shifted_offset_p_fv8hf"
>> [(match_operand:V8HI 0 "memory_operand" "=Us")
>> (match_operand:V8HI 1 "s_register_operand" "w")
>> (match_operand:V8HF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")
>> + (match_operand:V8BI 3 "vpr_register_operand" "Up")
>> (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -8666,7 +8666,7 @@ (define_insn
>> "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V8HI 1 "s_register_operand" "w")
>> (match_operand:V8HF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V8BI 3 "vpr_register_operand" "Up")]
>> VSTRHQSSO_F))]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]"
>> @@ -8703,7 +8703,7 @@ (define_insn "mve_vstrwq_scatter_base_p_fv4sf"
>> [(match_operand:V4SI 0 "s_register_operand" "w")
>> (match_operand:SI 1 "immediate_operand" "i")
>> (match_operand:V4SF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWQSB_F))
>> ]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> @@ -8752,7 +8752,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_fv4sf"
>> [(match_operand:V4SI 0 "mve_scatter_memory")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:V4SF 2 "s_register_operand")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -8770,7 +8770,7 @@ (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:V4SF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWQSO_F))]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> "vpst\;vstrwt.32\t%q2, [%0, %q1]"
>> @@ -8783,7 +8783,7 @@ (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si"
>> [(match_operand:V4SI 0 "mve_scatter_memory")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:V4SI 2 "s_register_operand")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
>> "TARGET_HAVE_MVE"
>> {
>> @@ -8801,7 +8801,7 @@ (define_insn
>> "mve_vstrwq_scatter_offset_p_<supf>v4si_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWSOQ))]
>> "TARGET_HAVE_MVE"
>> "vpst\;vstrwt.32\t%q2, [%0, %q1]"
>> @@ -8870,7 +8870,7 @@ (define_expand
>> "mve_vstrwq_scatter_shifted_offset_p_fv4sf"
>> [(match_operand:V4SI 0 "mve_scatter_memory")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:V4SF 2 "s_register_operand")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -8889,7 +8889,7 @@ (define_insn
>> "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:V4SF 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWQSSO_F))]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
>> @@ -8902,7 +8902,7 @@ (define_expand
>> "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si"
>> [(match_operand:V4SI 0 "mve_scatter_memory")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:V4SI 2 "s_register_operand")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
>> "TARGET_HAVE_MVE"
>> {
>> @@ -8921,7 +8921,7 @@ (define_insn
>> "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn"
>> [(match_operand:SI 0 "register_operand" "r")
>> (match_operand:V4SI 1 "s_register_operand" "w")
>> (match_operand:V4SI 2 "s_register_operand" "w")
>> - (match_operand:HI 3 "vpr_register_operand" "Up")]
>> + (match_operand:V4BI 3 "vpr_register_operand" "Up")]
>> VSTRWSSOQ))]
>> "TARGET_HAVE_MVE"
>> "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
>> @@ -9388,7 +9388,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
>> [(match_operand:V4SI 1 "s_register_operand" "0")
>> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
>> (match_operand:V4SI 3 "s_register_operand" "w")
>> - (match_operand:HI 4 "vpr_register_operand")]
>> + (match_operand:V4BI 4 "vpr_register_operand")]
>> VSTRWSBWBQ))
>> (set (match_operand:V4SI 0 "s_register_operand" "=w")
>> (unspec:V4SI [(match_dup 1) (match_dup 2)]
>> @@ -9439,7 +9439,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
>> [(match_operand:V4SI 1 "s_register_operand" "0")
>> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
>> (match_operand:V4SF 3 "s_register_operand" "w")
>> - (match_operand:HI 4 "vpr_register_operand")]
>> + (match_operand:V4BI 4 "vpr_register_operand")]
>> VSTRWQSBWB_F))
>> (set (match_operand:V4SI 0 "s_register_operand" "=w")
>> (unspec:V4SI [(match_dup 1) (match_dup 2)]
>> @@ -9563,7 +9563,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si"
>> [(match_operand:V4SI 0 "s_register_operand")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:SI 2 "mve_vldrd_immediate")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
>> "TARGET_HAVE_MVE"
>> {
>> @@ -9578,7 +9578,7 @@ (define_expand
>> "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
>> [(match_operand:V4SI 0 "s_register_operand")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:SI 2 "mve_vldrd_immediate")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
>> "TARGET_HAVE_MVE"
>> {
>> @@ -9597,7 +9597,7 @@ (define_insn
>> "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn"
>> [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
>> (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
>> (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
>> - (match_operand:HI 4 "vpr_register_operand" "Up")
>> + (match_operand:V4BI 4 "vpr_register_operand" "Up")
>> (mem:BLK (scratch))]
>> VLDRWGBWBQ))
>> (set (match_operand:V4SI 1 "s_register_operand" "=&w")
>> @@ -9671,7 +9671,7 @@ (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf"
>> [(match_operand:V4SI 0 "s_register_operand")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:SI 2 "mve_vldrd_immediate")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -9687,7 +9687,7 @@ (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf"
>> [(match_operand:V4SF 0 "s_register_operand")
>> (match_operand:V4SI 1 "s_register_operand")
>> (match_operand:SI 2 "mve_vldrd_immediate")
>> - (match_operand:HI 3 "vpr_register_operand")
>> + (match_operand:V4BI 3 "vpr_register_operand")
>> (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
>> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
>> {
>> @@ -9706,7 +9706,7 @@ (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn"
>> [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
>> (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
>> (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
>> - (match_operand:HI 4 "vpr_register_operand" "Up")
>> + (match_operand:V4BI 4 "vpr_register_operand" "Up")
>> (mem:BLK (scratch))]
>> VLDRWQGBWB_F))
>> (set (match_operand:V4SI 1 "s_register_operand" "=&w")
