Hello, I've just committed the attached patch as obvious.
Cheers, Oleg 2012-02-26 Oleg Endo <olege...@gcc.gnu.org> * config/sh/predicates.md: Remove blank lines. * config/sh/sh.c: Fix typos in comments. * config/sh/constraints.md: Likewise. * config/sh/sh.md: Remove blank lines. Fix typos in comments. Use ;; as comment characters.
Index: gcc/config/sh/predicates.md =================================================================== --- gcc/config/sh/predicates.md (revision 184582) +++ gcc/config/sh/predicates.md (working copy) @@ -448,7 +448,6 @@ return general_operand (op, mode); }) - ;; Returns 1 if OP is a POST_INC on stack pointer register. (define_predicate "sh_no_delay_pop_operand" @@ -466,7 +465,6 @@ return 0; }) - ;; Returns 1 if OP is a MEM that can be source of a simple move operation. (define_predicate "unaligned_load_operand" Index: gcc/config/sh/sh.c =================================================================== --- gcc/config/sh/sh.c (revision 184582) +++ gcc/config/sh/sh.c (working copy) @@ -1850,7 +1850,7 @@ } /* ??? How should we distribute probabilities when more than one branch - is generated. So far we only have soem ad-hoc observations: + is generated. So far we only have some ad-hoc observations: - If the operands are random, they are likely to differ in both parts. - If comparing items in a hash chain, the operands are random or equal; operation should be EQ or NE. @@ -5380,7 +5380,7 @@ /* If relaxing, generate pseudo-ops to associate function calls with the symbols they call. It does no harm to not generate these - pseudo-ops. However, when we can generate them, it enables to + pseudo-ops. However, when we can generate them, it enables the linker to potentially relax the jsr to a bsr, and eliminate the register load and, possibly, the constant pool entry. */ @@ -9259,7 +9259,7 @@ #if 0 /* If this is a label that existed before reload, then the register - if dead here. However, if this is a label added by reorg, then + is dead here. However, if this is a label added by reorg, then the register may still be live here. We can't tell the difference, so we just ignore labels completely. */ if (code == CODE_LABEL) @@ -9569,7 +9569,7 @@ { int size; - /* Check if this the address of an unaligned load / store. */ + /* Check if this is the address of an unaligned load / store. */ if (mode == VOIDmode) return CONST_OK_FOR_I06 (INTVAL (op)); Index: gcc/config/sh/constraints.md =================================================================== --- gcc/config/sh/constraints.md (revision 184582) +++ gcc/config/sh/constraints.md (working copy) @@ -139,7 +139,7 @@ (match_test "ival >= 0 && ival <= 255"))) (define_constraint "K12" - "An unsigned 8-bit constant, as used in SH2A 12-bit display." + "An unsigned 8-bit constant, as used in SH2A 12-bit displacement addressing." (and (match_code "const_int") (match_test "ival >= 0 && ival <= 4095"))) Index: gcc/config/sh/sh.md =================================================================== --- gcc/config/sh/sh.md (revision 184582) +++ gcc/config/sh/sh.md (working copy) @@ -4405,8 +4405,6 @@ "sub r63, %1, %0" [(set_attr "type" "arith_media")]) - - ;; Don't expand immediately because otherwise neg:DI (abs:DI) will not be ;; combined. (define_expand "negdi2" @@ -4497,7 +4495,6 @@ DONE; }") - ;; The SH4 202 can do zero-offset branches without pipeline stalls. ;; This can be used as some kind of conditional execution, which is useful ;; for abs. @@ -5468,7 +5465,7 @@ operands[3] = gen_rtx_REG (DImode, REGNO (operands[2])); }") -/* When storing r0, we have to avoid reg+reg addressing. */ +;; When storing r0, we have to avoid reg+reg addressing. (define_insn "movhi_i" [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r") (match_operand:HI 1 "general_movsrc_operand" "Q,rI08,m,t,r,l,r,i"))] @@ -7472,7 +7469,7 @@ (set_attr "fp_set" "unknown")]) ;; This is TBR relative jump instruction for SH2A architecture. -;; Its use is enabled assigning an attribute "function_vector" +;; Its use is enabled by assigning an attribute "function_vector" ;; and the vector number to a function during its declaration. (define_insn "call_valuei_tbr_rel" @@ -9581,8 +9578,6 @@ DONE; ") - - ;; sne moves the complement of the T reg to DEST like this: ;; cmp/eq ... ;; mov #-1,temp @@ -9605,7 +9600,6 @@ operands[1] = gen_reg_rtx (SImode); }") - ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1. ;; This prevents a regression that occurred when we switched from xor to ;; mov/neg for sne. @@ -9659,7 +9653,6 @@ DONE; ") - ;; ------------------------------------------------------------------------- ;; Instructions to cope with inline literal tables ;; ------------------------------------------------------------------------- @@ -12688,7 +12681,7 @@ [(set_attr "type" "arith_media") (set_attr "highpart" "ignore")]) -/* These are useful to expand ANDs and as combiner patterns. */ +;; These are useful to expand ANDs and as combiner patterns. (define_insn_and_split "mshfhi_l_di" [(set (match_operand:DI 0 "arith_reg_dest" "=r,f") (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f")