On Thu, Sep 16, 2021 at 11:21 AM Richard Earnshaw via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 16/09/2021 10:12, Christophe LYON via Gcc-patches wrote:
> >
> > On 15/09/2021 18:43, Richard Earnshaw via Gcc-patches wrote:
> >>
> >>
> >> On 15/09/2021 17:13, Christophe Lyon via Gcc-patches wrote:
> >>> On Wed, Sep 15, 2021 at 2:49 PM Richard Earnshaw via Gcc-patches <
> >>> gcc-patches@gcc.gnu.org> wrote:
> >>>
> >>>>
> >>>>
> >>>> On 15/09/2021 13:26, Christophe LYON via Gcc-patches wrote:
> >>>>>
> >>>>> On 15/09/2021 13:02, Richard Earnshaw wrote:
> >>>>>>
> >>>>>>
> >>>>>> On 26/08/2021 16:53, Christophe Lyon via Gcc-patches wrote:
> >>>>>>> g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
> >>>>>>> double-precision FPU support, but does not make sure it is actually
> >>>>>>> supported by the target.
> >>>>>>> Check (__ARM_FP & 8) to ensure this.
> >>>>>>>
> >>>>>>> 2021-08-26 Christophe Lyon <christophe.l...@foss.st.com>
> >>>>>>>
> >>>>>>> gcc/testsuite/
> >>>>>>> * g++.dg/eh/arm-vfp-unwind.C: Check __ARM_FP.
> >>>>>>> ---
> >>>>>>> gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C | 2 +-
> >>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>>>>
> >>>>>>> diff --git a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C
> >>>>>>> b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C
> >>>>>>> index 62263c0c3b0..90d20081d78 100644
> >>>>>>> --- a/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C
> >>>>>>> +++ b/gcc/testsuite/g++.dg/eh/arm-vfp-unwind.C
> >>>>>>> @@ -3,7 +3,7 @@
> >>>>>>> /* Test to catch off-by-one errors in arm/pr-support.c. */
> >>>>>>> -#if defined (__VFP_FP__) && !defined (__SOFTFP__)
> >>>>>>> +#if defined (__VFP_FP__) && !defined (__SOFTFP__) && (__ARM_FP &
> 8)
> >>>>>>> #include <iostream>
> >>>>>>> #include <stdlib.h>
> >>>>>>>
> >>>>>>
> >>>>>> Wouldn't it be better to have an alternate to the asm for the case
> >>>>>> where we only have single-precision float? Something like
> >>>>>> (untested):
> >>>>>>
> >>>>>> static void donkey ()
> >>>>>> {
> >>>>>> #if __ARM_FP & 8
> >>>>>> asm volatile ("fcpyd d9, %P0" : : "w" (1.2345) : "d9");
> >>>>>> #else
> >>>>>> asm volatile ("fcpys s18, %P0" : : "w" (1.2345f) : "s18");
> >>>>>> #endif
> >>>>>> throw 1;
> >>>>>> }
> >>>>>
> >>>>>
> >>>>> I tried similar things but they failed on some testing
> configurations.
> >>>>>
> >>>>> Let me try your version, I'll let you know if there is any fallout.
> >>>>
> >>>> Of course, the asm syntax should be converted to the new 'unified
> >>>> syntax' form ie vmov.f{32,64}.
> >>>>
> >>>>
> >>> The problem is that %P expects a double-precision register.
> >>> It seems there's nothing to print a single-precision register, or
> >>> rather %p
> >>> (small p)
> >>> rejects s18 too.
> >>>
> >>>
> >> I said it was untested :)
> >
> > In fact, I now remember I tried similar things and everything failed,
> > hence my proposal at the start of this thread :-)
> >
> >
> >>
> >> You want something like
> >>
> >> #if __ARM_FP & 8
> >> asm volatile ("vmov.f64 d9, %P0" : : "w" (1.2345) : "d9");
> >> #else
> >> asm volatile ("vmov.f32 s18, %0" : : "t" (1.2345f) : "s18");
> >> #endif
> >>
> >> (there's no need for a modifier on the single-precision register name).
> >
> > Ha! I missed the magic "t".
> >
> > I confirm this fixes the issues that motivated my original patch.
> >
> > Do you want me to commit it?
>
> Yes, please.
>
> Ack, done as r12-3571-g8e2c293f02745d47948fff19615064e4b34c1776
R.
>
> >
> >
> > Thanks
> >
> > Christophe
> >
> >
> >>
> >>>
> >>>> R.
> >>>>
> >>>>>
> >>>>> Christophe
> >>>>>
> >>>>>
> >>>>>>
> >>>>>> R.
> >>>>
>
